公开(公告)号：JP2012209552A

公开(公告)日：2012-10-25

申请号：JP2012064435

申请日：2012-03-21

Applicant: Renesas Electronics Corp ,  Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  ルネサスエレクトロニクス株式会社

Inventor： SODA EIICHI ,  YIN YUN-PENG ,  SIVANANDA KANAKASABAPATHY

IPC: H01L21/768 ,  H01L21/3065

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897

Abstract: PROBLEM TO BE SOLVED: To improve a wiring form of a semiconductor device.SOLUTION: A method of manufacturing a semiconductor device includes: a step in which a first mask containing a first pattern that specifies a groove region is formed on a metal film provided to an inter-layer film of the semiconductor device by transferring of a side wall form; a step of forming a second pattern by forming a second mask having at least one opening that overlaps with the first pattern so that, when viewed from above, the second mask overlaps with the first mask and the opening overlaps with the groove region; a step in which the inter-layer film is etched through the first and second masks so that the first pattern is transferred to the inter-layer film; and a step of transferring the second pattern to the inter-layer film by etching the inter-layer film through the second mask. Here, the first pattern is formed at the inter-layer film with a depth different from the second pattern.

Abstract translation: 要解决的问题：改进半导体器件的布线形式。 解决方案：一种制造半导体器件的方法包括：一个步骤，其中包含指定沟槽区域的第一图案的第一掩模形成在通过转移所述半导体器件的层间膜的金属膜上 侧壁形式; 通过形成具有与第一图案重叠的至少一个开口的第二掩模形成第二图案的步骤，使得当从上方观察时，第二掩模与第一掩模重叠，并且开口与槽区重叠; 通过第一和第二掩模蚀刻层间膜，使得第一图案被转印到层间膜的步骤; 以及通过经由第二掩模蚀刻层间膜而将第二图案转印到层间膜的步骤。 这里，第一图案形成在具有与第二图案不同的深度的层间膜。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：GB2579463B

公开(公告)日：2022-03-02

申请号：GB202001032

申请日：2018-06-25

Applicant: IBM

Inventor： GAURI KARVE ,  PIETRO MONTANINI ,  ERIC MILLER ,  SIVANANDA KANAKASABAPATHY ,  ANDREW GREENE

IPC: H01L21/8238 ,  H01L29/78

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

公开(公告)号：GB2579463A

公开(公告)日：2020-06-24

申请号：GB202001032

申请日：2018-06-25

Applicant: IBM

Inventor： GAURI KARVE ,  PIETRO MONTANINI ,  ERIC MILLER ,  SIVANANDA KANAKASABAPATHY ,  ANDREW GREENE

IPC: H01L21/8238 ,  H01L29/78

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

公开(公告)号：GB2556224B

公开(公告)日：2019-10-30

申请号：GB201720310

申请日：2016-05-06

Applicant: IBM

Inventor： SIVANANDA KANAKASABAPATHY ,  FEE LI LIE ,  GAURI KARVE ,  SOON-CHEON SEO ,  STUART SIEG ,  HONG HE ,  DERRICK LIU ,  BRUCE DORIS

IPC: H01L21/336 ,  H01L29/78

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：GB2556224A

公开(公告)日：2018-05-23

申请号：GB201720310

申请日：2016-05-06

Applicant: IBM

Inventor： SIVANANDA KANAKASABAPATHY ,  FEE LI LIE ,  GAURI KARVE ,  SOON-CHEON SEO ,  STUART SIEG ,  HONG HE ,  DERRICK LIU ,  BRUCE DORIS

IPC: H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion (14P) having an end wall (15W) and extending upward from a substrate (10). A gate structure (16) straddles a portion of the semiconductor fin portion (14P). A first set of gate spacers (24P/50P) is located on opposing sidewall surfaces of the gate structure (16L/16R); and a second set of gate spacers (32P) is located on sidewalls of the first set of gate spacers (24P/50P). One gate spacer of the second set of spacers (32P) has a lower portion that directly contacts the end wall (15W) of the semiconductor fin portion (14P).