公开(公告)号：GB2579463B

公开(公告)日：2022-03-02

申请号：GB202001032

申请日：2018-06-25

Applicant: IBM

Inventor： GAURI KARVE ,  PIETRO MONTANINI ,  ERIC MILLER ,  SIVANANDA KANAKASABAPATHY ,  ANDREW GREENE

IPC: H01L21/8238 ,  H01L29/78

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

公开(公告)号：GB2579463A

公开(公告)日：2020-06-24

申请号：GB202001032

申请日：2018-06-25

Applicant: IBM

Inventor： GAURI KARVE ,  PIETRO MONTANINI ,  ERIC MILLER ,  SIVANANDA KANAKASABAPATHY ,  ANDREW GREENE

IPC: H01L21/8238 ,  H01L29/78

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).