公开(公告)号：GB2577417B

公开(公告)日：2021-09-08

申请号：GB201917399

申请日：2018-05-10

Applicant: IBM

Inventor： MARC BERGENDAHL ,  ERIC MILLER ,  FEE LI LIE ,  SEAN TEEHAN ,  KANGGUO CHENG ,  JOHN RYAN SPORRE ,  GAURI KARVE

IPC: H01L27/04

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：GB2577417A

公开(公告)日：2020-03-25

申请号：GB201917399

申请日：2018-05-10

Applicant: IBM

Inventor： MARC BERGENDAHL ,  ERIC MILLER ,  FEE LI LIE ,  SEAN TEEHAN ,  KANGGUO CHENG ,  JOHN RYAN SPORRE ,  GAURI KARVE

IPC: H01L27/04

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：GB2600338A

公开(公告)日：2022-04-27

申请号：GB202201027

申请日：2020-07-03

Applicant: IBM

Inventor： STUART SIEG ,  DANIEL JAMES DECHENE ,  ERIC MILLER

IPC: H01L21/02

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.

公开(公告)号：GB2579463B

公开(公告)日：2022-03-02

申请号：GB202001032

申请日：2018-06-25

Applicant: IBM

Inventor： GAURI KARVE ,  PIETRO MONTANINI ,  ERIC MILLER ,  SIVANANDA KANAKASABAPATHY ,  ANDREW GREENE

IPC: H01L21/8238 ,  H01L29/78

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

公开(公告)号：GB2579463A

公开(公告)日：2020-06-24

申请号：GB202001032

申请日：2018-06-25

Applicant: IBM

Inventor： GAURI KARVE ,  PIETRO MONTANINI ,  ERIC MILLER ,  SIVANANDA KANAKASABAPATHY ,  ANDREW GREENE

IPC: H01L21/8238 ,  H01L29/78

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).