公开(公告)号：JP2000339216A

公开(公告)日：2000-12-08

申请号：JP2000124596

申请日：2000-04-25

Applicant: IBM

Inventor： DELL TIMOTHY J ,  HAZELZET BRUCE G ,  KELLOGG MARK W ,  MILLER CHRISTOPHER P

IPC: G06F1/32 ,  G06F12/02 ,  G06F12/06 ,  G11C11/403

Abstract: PROBLEM TO BE SOLVED: To provide an improved memory module with a signal processing element, preferably a DSP, at least one bank of a memory chip, preferably first and second banks to be individually addressed and its use in a computer system. SOLUTION: The memory module 8 is provided with first and second banks 12, 13 to be respectively addressed of the DSP of the memory chip. The first bank is constituted so as to basically function under control of the signal processing element 36, the second bank is constituted so as to basically function under control of a system memory controller 28, however, all parts of respective memory banks are addressed by both of the signal processing element and the system memory controller. Both banks of the memory chip is placed on at least one high power state and at least one low power state by either of the system memory controller or the DSP.

公开(公告)号：DE68923828D1

公开(公告)日：1995-09-21

申请号：DE68923828

申请日：1989-05-17

Applicant: IBM

Inventor： ARLINGTON DAVID L ,  COLE JACQUELINE MORRIS ,  HAZELZET BRUCE G ,  KROLAK DAVID J ,  LI HEHCHING HARRY ,  OZA BHARAT J ,  WEAVER A FRANK

IPC: G06F12/16 ,  G06F11/10 ,  G06F12/06 ,  G06F13/16

Abstract: A "smart" memory card architecture and interface provides significantly increased performance, in part, by using fast access dynamic random access memory (DRAM) technologies which allows up to 8-byte data transfers from the memory card every 27ns after the initial access. The 27ns transfer rate includes the time required for error correction code (ECC), parity generation, and other reliability functions. Only two complementary metal oxide semiconductor (CMOS) integrated circuit (IC) logic chips or modules provide all the function required. The simplicity and flexibility afforded by the "smart" memory card approach provides a means to allow one card interface to be used with a broad range of hardware technologies and in different systems. The architecture of the memory card provides a full range of direct and partial store operations in a manner transparent to the system.

公开(公告)号：DE68923828T2

公开(公告)日：1996-03-28

申请号：DE68923828

申请日：1989-05-17

Applicant: IBM

Inventor： ARLINGTON DAVID L ,  COLE JACQUELINE MORRIS ,  HAZELZET BRUCE G ,  KROLAK DAVID J ,  LI HEHCHING HARRY ,  OZA BHARAT J ,  WEAVER A FRANK

IPC: G06F12/16 ,  G06F11/10 ,  G06F12/06 ,  G06F13/16

Abstract: A "smart" memory card architecture and interface provides significantly increased performance, in part, by using fast access dynamic random access memory (DRAM) technologies which allows up to 8-byte data transfers from the memory card every 27ns after the initial access. The 27ns transfer rate includes the time required for error correction code (ECC), parity generation, and other reliability functions. Only two complementary metal oxide semiconductor (CMOS) integrated circuit (IC) logic chips or modules provide all the function required. The simplicity and flexibility afforded by the "smart" memory card approach provides a means to allow one card interface to be used with a broad range of hardware technologies and in different systems. The architecture of the memory card provides a full range of direct and partial store operations in a manner transparent to the system.