公开(公告)号：DE2041343A1

公开(公告)日：1971-03-18

申请号：DE2041343

申请日：1970-08-20

Applicant: IBM

Inventor： PHILLIP CASTRUCCI PAUL ,  ROGENE GATES HARLAN ,  ATHANASIUS HENLE ROBERT ,  DAVID PRICER WILBUR ,  MICHAEL MORTON ROBERT ,  WESTLEY MASON JOHN ,  DAVID NORTH WILLIAM

IPC: F22B21/06 ,  G11C17/06 ,  G11C17/14 ,  G11C17/16 ,  H01L23/525 ,  H01L27/00 ,  H01L27/102 ,  G11C17/00

Abstract: A read only memory having the capability of being written into once after manufacture. The cells of the memory are capable of being fused or permanently altered by directing a fusing current to the selected cells. The cell is a monolithic semiconductor device comprising a diode to be biased in a forward direction and a diode to be biased in the reverse direction structured so as to form back-to-back diodes. The reverse diode has a lower reverse breakdown voltage than the forward diode, and a metal connection, unconnected to any remaining circuit elements contacts the semiconductor device between diode junctions. The fusing current causes a metal-semiconductor alloy to form and short out the reverse diode.

公开(公告)号：DE2001697A1

公开(公告)日：1970-07-23

申请号：DE2001697

申请日：1970-01-15

Applicant: IBM

Inventor： ATHANASIUS HENLE ROBERT

IPC: G11C8/00 ,  G11C8/10 ,  G11C11/414 ,  H03M7/00 ,  G11C5/02

Abstract: 1,272,551. Data storage. INTERNATIONAL BUSINESS MACHINES CORP. 9 Jan., 1970 [15 Jan., 1969], No. 1065/70. Heading G4C. A memory device comprises a plurality of storage cells, addressing means, decoding means to address one of the cells for reading or writing, the decoding means including a main decoder connected to the addressing means and a first group of decoders each connected to the main decoder and to the addressing means, such that when power is supplied to the main decoder in response to a signal from the addressing means the main decoder supplies to only one of the first group of decoders a signal in response to which power is selectively supplied to only that one decoder. The addressing means (an address register) enables the power supply to the main decoder to cause it to decode 3 address bits to enable the power supply to one of 8 decoders of the first group. This decoder decodes 3 further address bits (supplied to all decoders of the first group) to enable the power supply of one of 8 decoders of a second group which decodes 6 further address bits (supplied to all the decoders of the second group) to address one of 8 x 8 x 64 storage cells (or words). The power supplies are enabled using transistors and three variants are shown of this. The first group of decoders could address the memory directly, the second group being omitted. The invention reduces power consumption and heat problems in semi-conductor -monolithic memories and magnetic memories.