公开(公告)号：EP1378090A4

公开(公告)日：2005-02-09

申请号：EP02723233

申请日：2002-02-25

Applicant: IBM

Inventor： BARRETT WAYNE M ,  CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  JACKSON RORY D ,  KOPCSAY GERARD V ,  NATHANSON BEN J ,  TAKKEN TODD E ,  VRANAS PAVLOS M

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  H04L7/00 ,  H03D3/24 ,  H04B10/08

CPC classification number: H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338 ,  Y02B30/746

Abstract: A fan module including: two or more individual fans, each fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each of the two or more individual fans; a temperature sensor for sensing a temperature associated with the two or more fans and for outputting a first signal corresponding to the temperature; rotational speed sensor for outputting a second signal corresponding to a rotational speed of each of the two or more fans; and a processor for receiving the first and second signals and controlling the two or more individual fans based on the first and second signals.

公开(公告)号：JP2007293845A

公开(公告)日：2007-11-08

申请号：JP2007106709

申请日：2007-04-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BARRETT WAYNE M ,  GREENFIELD TODD A

IPC: G06F13/42 ,  G06F1/06

CPC classification number: G06F13/385 ,  H03K5/135 ,  H03M9/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for allowing a plurality of devices to read data from a serial data source in a parallel format in a minimum waiting time. SOLUTION: Data from the serial data source is deserialized by placing a plurality of predefined units of data onto a parallel bus and asserting a deserialization clock when each of the plurality of predefined units of data is valid on the parallel bus. A delayed clock pulse is generated after a predetermined amount of time after each assertion of the deserialization clock. Each delayed pulse is repeated so as to generate an end point repeated clock pulse corresponding to each delayed pulse wherein the predetermined amount of time is an amount of time that ensures that each predefined unit of data on the parallel bus is valid when each end point repeated clock pulse is asserted. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种允许多个设备在最小等待时间内以并行格式从串行数据源读取数据的方法。 解决方案：串行数据源的数据通过将多个预定义的数据单元放置在并行总线上来反序列化，并且当并行总线上的多个预定义数据单元中的每一个都有效时，断言反序列化时钟。 在每次断言反序列化时钟之后的预定时间量之后产生延迟的时钟脉冲。 重复每个延迟脉冲，以便产生对应于每个延迟脉冲的终点重复时钟脉冲，其中预定量的时间是确保每个终点重复时并行总线上的每个预定义的数据单元有效的时间量 时钟脉冲被断言。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：CA2436412A1

公开(公告)日：2002-09-06

申请号：CA2436412

申请日：2002-02-25

Applicant: IBM

Inventor： GARA ALAN G ,  COTEUS PAUL W ,  JACKSON RORY D ,  KOPCSAY GERARD V ,  VRANAS PAVLOS M ,  TAKKEN TODD E ,  NATHANSON BEN J ,  BARRETT WAYNE M ,  CHEN DONG

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  H04L7/00 ,  H04B10/08 ,  H03D3/24

Abstract: A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as i s done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays (Fig. 5) for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.

公开(公告)号：DE60221235T2

公开(公告)日：2008-04-10

申请号：DE60221235

申请日：2002-02-25

Applicant: IBM

Inventor： BARRETT WAYNE M ,  CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  JACKSON RORY D ,  KOPCSAY GERARD V ,  NATHANSON BEN J ,  TAKKEN TODD E ,  VRANAS PAVLOS M

IPC: G06F11/10 ,  H04L7/00 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H03D3/24 ,  H04B10/08 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.

公开(公告)号：DE60221235D1

公开(公告)日：2007-08-30

申请号：DE60221235

申请日：2002-02-25

Applicant: IBM

Inventor： BARRETT WAYNE M ,  CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  JACKSON RORY D ,  KOPCSAY GERARD V ,  NATHANSON BEN J ,  TAKKEN TODD E ,  VRANAS PAVLOS M

IPC: G06F11/10 ,  H04L7/00 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H03D3/24 ,  H04B10/08 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.