公开(公告)号：GB2544587A

公开(公告)日：2017-05-24

申请号：GB201615020

申请日：2016-09-05

Applicant: IBM

Inventor： BULENT ABALI ,  BARTHOLOMEW BLANER ,  HUBERTUS FRANKE ,  JOHN JOSEPH REILLY

IPC: H03M7/42

Abstract: Techniques for creating a dynamic Huffman table in hardware are provided. The method includes the steps of: implementing dynamic Huffman tables in hardware representing a plurality of Huffman tree shapes pre-computed from a sample data set, wherein the Huffman tree shapes are represented in the dynamic Huffman tables by code length values; upon receipt of input data, writing symbols and their counts from the input data to the dynamic Huffman tables; calculating a score for each of the dynamic Huffman tables with the symbols and counts from the input data, wherein the score is based on the code length values of the pre-computed Huffman tree shapes and the counts from the input data; and selecting a given one of the dynamic Huffman tables having a lowest score for encoding the input data. The score may be based on a sum of products of pre-computed code length values and counts from the input data. A process for implementing the present techniques in SRAM is also provided. The use of pre-computed tables simplifies the hardware.

公开(公告)号：GB2572287B

公开(公告)日：2020-03-04

申请号：GB201909219

申请日：2017-11-27

Applicant: IBM

Inventor： LAKSHMINARAYANA BABA ARIMILLI ,  WILLIAM STARKE ,  YIFTACH BENJAMINI ,  JEFFREY A STUECHELI ,  BARTHOLOMEW BLANER ,  ETAI ADAR

IPC: G06F12/0815 ,  G06F12/1081 ,  G06F13/16

Abstract: Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.

公开(公告)号：GB2572287A8

公开(公告)日：2019-10-09

申请号：GB201909219

申请日：2017-11-27

Applicant: IBM

Inventor： LAKSHMINARAYANA ARIMILLI ,  WILLIAM STARKE ,  YIFTACH BENJAMINI ,  JEFFREY A STUECHELI ,  BARTHOLOMEW BLANER ,  ETAI ADAR

IPC: G06F12/0815 ,  G06F12/1081 ,  G06F13/16

Abstract: Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.

公开(公告)号：GB2572287A

公开(公告)日：2019-09-25

申请号：GB201909219

申请日：2017-11-27

Applicant: IBM

Inventor： LAKSHMINARAYANA ARIMILLI ,  WILLIAM STARKE ,  YIFTACH BENJAMINI ,  JEFFREY A STUECHELI ,  BARTHOLOMEW BLANER ,  ETAI ADAR

IPC: G06F12/0815 ,  G06F12/1081 ,  G06F13/16

Abstract: Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.

公开(公告)号：GB2544587B

公开(公告)日：2018-02-07

申请号：GB201615020

申请日：2016-09-05

Applicant: IBM

Inventor： BULENT ABALI ,  BARTHOLOMEW BLANER ,  HUBERTUS FRANKE ,  JOHN JOSEPH REILLY

IPC: H03M7/42