公开(公告)号：GB2572287A

公开(公告)日：2019-09-25

申请号：GB201909219

申请日：2017-11-27

Applicant: IBM

Inventor： LAKSHMINARAYANA ARIMILLI ,  WILLIAM STARKE ,  YIFTACH BENJAMINI ,  JEFFREY A STUECHELI ,  BARTHOLOMEW BLANER ,  ETAI ADAR

IPC: G06F12/0815 ,  G06F12/1081 ,  G06F13/16

Abstract: Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.

公开(公告)号：GB2515928B

公开(公告)日：2018-08-08

申请号：GB201416684

申请日：2013-02-25

Applicant: IBM

Inventor： ILYA GRANOVSKY ,  ETAI ADAR

IPC: G06F13/42 ,  G06F13/38

Abstract: An apparatus and method of fast PCIe multi-function device address decode utilizing a target function data look up table. One or more decode directives (e.g., targeted functions) are provided within the PCIe request packet, thereby eliminating the need for target function search during the decode process in the endpoint device. This enables single-decoder single-step decode implementation in complex multi-function devices.

公开(公告)号：GB2572287B

公开(公告)日：2020-03-04

申请号：GB201909219

申请日：2017-11-27

Applicant: IBM

Inventor： LAKSHMINARAYANA BABA ARIMILLI ,  WILLIAM STARKE ,  YIFTACH BENJAMINI ,  JEFFREY A STUECHELI ,  BARTHOLOMEW BLANER ,  ETAI ADAR

IPC: G06F12/0815 ,  G06F12/1081 ,  G06F13/16

Abstract: Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.

公开(公告)号：GB2572287A8

公开(公告)日：2019-10-09

申请号：GB201909219

申请日：2017-11-27

Applicant: IBM

Inventor： LAKSHMINARAYANA ARIMILLI ,  WILLIAM STARKE ,  YIFTACH BENJAMINI ,  JEFFREY A STUECHELI ,  BARTHOLOMEW BLANER ,  ETAI ADAR

IPC: G06F12/0815 ,  G06F12/1081 ,  G06F13/16

Abstract: Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.