公开(公告)号：JP2007287142A

公开(公告)日：2007-11-01

申请号：JP2007099225

申请日：2007-04-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JEFFREY A STUECHELI ,  STARKE WILLIAM JOHN ,  JAMES S FIELDS JR ,  GOODMAN BENJIMAN LEE ,  LEO J CLARK

IPC: G06F15/80 ,  G06F15/173

CPC classification number: G06F12/0831 ,  G06F12/0897 ,  G06F12/1458

Abstract: PROBLEM TO BE SOLVED: To provide an interconnect fabric for a data processing system for saving a bandwidth favorably and improving performance of the whole system. SOLUTION: The data processing system is provided with a plurality of processors coupled by a plurality of communication links for point-to-point communication so that at least a few of communication among a plurality of processing apparatuses out of processors 100 are transmitted via at least one intermediate processor among the plurality of processors. The intermediate processor is provided with: one or more masters for starting a first operation; a snooper for receiving a second operation started by another processor among a plurality of processors; a physical queue for storing the master tag of the first operation started by one or more masters in one of the processors; and a ticket issuing mechanism for assigning to the second operation observed in the intermediate processor a ticket number which indicates the order of observation relative to other second operation. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供用于数据处理系统的互连结构，用于有利地节省带宽并提高整个系统的性能。 解决方案：数据处理系统设置有多个处理器，其通过多个通信链路耦合用于点对点通信，使得在处理器100中的多个处理装置中的至少少数通信被传送 经由多个处理器中的至少一个中间处理器。 中间处理器具有：用于开始第一操作的一个或多个主器件; 用于接收由多个处理器中的另一处理器开始的第二操作的窥探者; 用于存储由一个或多个处理器中的一个处理器中的一个或多个主器件启动的第一操作的主标签的物理队列; 以及票据发行机构，用于将在中间处理器中观察到的第二操作分配给指示相对于其他第二操作的观察次序的票号。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：GB2572287A

公开(公告)日：2019-09-25

申请号：GB201909219

申请日：2017-11-27

Applicant: IBM

Inventor： LAKSHMINARAYANA ARIMILLI ,  WILLIAM STARKE ,  YIFTACH BENJAMINI ,  JEFFREY A STUECHELI ,  BARTHOLOMEW BLANER ,  ETAI ADAR

IPC: G06F12/0815 ,  G06F12/1081 ,  G06F13/16

Abstract: Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.

公开(公告)号：GB2511986B

公开(公告)日：2020-03-04

申请号：GB201411244

申请日：2012-11-21

Applicant: IBM

Inventor： JEFFREY A STUECHELI ,  ERIC EUGENE RETTER ,  KARTHICK RAJAMANI ,  BRUCE MEALEY ,  JOHN BRUCE CARTER

IPC: G06F7/483 ,  G06F5/01

Abstract: Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

公开(公告)号：GB2572287B

公开(公告)日：2020-03-04

申请号：GB201909219

申请日：2017-11-27

Applicant: IBM

Inventor： LAKSHMINARAYANA BABA ARIMILLI ,  WILLIAM STARKE ,  YIFTACH BENJAMINI ,  JEFFREY A STUECHELI ,  BARTHOLOMEW BLANER ,  ETAI ADAR

IPC: G06F12/0815 ,  G06F12/1081 ,  G06F13/16

Abstract: Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.

公开(公告)号：GB2572287A8

公开(公告)日：2019-10-09

申请号：GB201909219

申请日：2017-11-27

Applicant: IBM

Inventor： LAKSHMINARAYANA ARIMILLI ,  WILLIAM STARKE ,  YIFTACH BENJAMINI ,  JEFFREY A STUECHELI ,  BARTHOLOMEW BLANER ,  ETAI ADAR

IPC: G06F12/0815 ,  G06F12/1081 ,  G06F13/16

Abstract: Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.