公开(公告)号：JP2006074780A

公开(公告)日：2006-03-16

申请号：JP2005251301

申请日：2005-08-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEUKEMA BRUCE L ,  DREHMEL ROBERT A ,  HALL WILLIAM E ,  KUESEL JAMIE R ,  PIVONIA GILAD ,  SHEARER ROBERT A

IPC: H04L9/10

CPC classification number: G06F21/72 ,  H04L9/06 ,  H04L63/123 ,  H04L2209/125

Abstract: PROBLEM TO BE SOLVED: To provide a mechanism to minimize latency impact of data to be decrypted.
SOLUTION: Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined to a decryption engine as it is received, thus allowing decryption to begin prior to validation. In some cases, the decryption engine may be notified of data transfer errors detected during the validation process, in order to prevent reporting false security violations.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种最小化待解密数据的延迟影响的机制。 提供了用于减少与解密加密数据相关联的延迟的影响的方法和装置。 而不是等到整个加密数据包被验证（例如，通过检查数据传输错误），加密的数据可以在被接收时被流水线化到解密引擎，从而允许在验证之前开始解密。 在一些情况下，可以向解密引擎通知在验证过程期间检测到的数据传输错误，以防止报告错误的安全违规。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：CA2273719C

公开(公告)日：2004-03-30

申请号：CA2273719

申请日：1999-06-04

Applicant: IBM

Inventor： FUHS RONALD E ,  BEUKEMA BRUCE L ,  THURBER STEVEN MARK ,  NEAL DANNY M ,  KELLEY RICHARD A

IPC: G06F13/40 ,  G06F3/00

Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 1 00 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking da ta on only one clock edge, or by clocking data on both a rising edge and a falling edge of a cloc k signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions o r alias split transactions to delayed transactions. Backward compatibility may also be provided for option al features such as hot-pluggability.

公开(公告)号：CA2273719A1

公开(公告)日：2000-01-15

申请号：CA2273719

申请日：1999-06-04

Applicant: IBM

Inventor： BEUKEMA BRUCE L ,  THURBER STEVEN MARK ,  NEAL DANNY M ,  FUHS RONALD E ,  KELLEY RICHARD A

IPC: G06F13/40 ,  G06F3/00

Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions or alias split transactions to delayed transactions. Backward compatibility may also be provided for optional features such as hot-pluggability.