公开(公告)号：CA2273719C

公开(公告)日：2004-03-30

申请号：CA2273719

申请日：1999-06-04

Applicant: IBM

Inventor： FUHS RONALD E ,  BEUKEMA BRUCE L ,  THURBER STEVEN MARK ,  NEAL DANNY M ,  KELLEY RICHARD A

IPC: G06F13/40 ,  G06F3/00

Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 1 00 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking da ta on only one clock edge, or by clocking data on both a rising edge and a falling edge of a cloc k signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions o r alias split transactions to delayed transactions. Backward compatibility may also be provided for option al features such as hot-pluggability.

公开(公告)号：CA2273719A1

公开(公告)日：2000-01-15

申请号：CA2273719

申请日：1999-06-04

Applicant: IBM

Inventor： BEUKEMA BRUCE L ,  THURBER STEVEN MARK ,  NEAL DANNY M ,  FUHS RONALD E ,  KELLEY RICHARD A

IPC: G06F13/40 ,  G06F3/00

Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions or alias split transactions to delayed transactions. Backward compatibility may also be provided for optional features such as hot-pluggability.