公开(公告)号：WO2011032866A3

公开(公告)日：2011-09-29

申请号：PCT/EP2010063153

申请日：2010-09-08

Applicant: IBM ,  IBM UK ,  KIRSCHT JOSEPH ALLEN ,  MCGLONE ELIZABETH ,  BLACKMON HERMAN LEE ,  HARADEN RYAN SCOTT

Inventor： KIRSCHT JOSEPH ALLEN ,  MCGLONE ELIZABETH ,  BLACKMON HERMAN LEE ,  HARADEN RYAN SCOTT

IPC: G06F11/14 ,  G06F13/16

CPC classification number: H04L1/1845 ,  G06F11/1443 ,  H04L2001/0092

Abstract: Systems and methods to respond to error detection are provided. A particular method may include issuing a first command to a first redrive device and a second command to a second redrive device. The method may also include reissuing the second command to the second redrive device in response to detecting a transmission error between a memory controller and the second redrive device. The method may further include storing at a first buffer first data that is received from the first redrive device in response to the first command. The method may include storing at a second buffer second data that is received from the second redrive device in response to the reissued second command. The method also may include merging the second data with the first data.

Abstract translation: 提供了响应错误检测的系统和方法。 特定的方法可以包括向第一驱动设备发出第一命令并向第二驱动设备发出第二命令。 该方法还可以包括响应于检测到存储器控制器和第二驱动器设备之间的传输错误而将第二命令重发到第二驱动器设备。 该方法还可以包括响应于第一命令将从第一驱动器设备接收到的第一数据存储在第一缓冲器中。 该方法可以包括响应于重新发布的第二命令，将从第二重驱动设备接收的第二数据存储在第二缓冲器中。 该方法还可以包括将第二数据与第一数据合并。

公开(公告)号：DE69502656D1

公开(公告)日：1998-07-02

申请号：DE69502656

申请日：1995-03-08

Applicant: IBM

Inventor： PAULSON PEDER JAMES ,  BLACKMON HERMAN LEE ,  HASELHORST KENT HAROLD ,  DREHMEL ROBERT ALLEN ,  KROLAK DAVID JOHN ,  GROSBACH LYLE EDWIN ,  MARCELLA JAMES ANTHONY

IPC: G06F13/42 ,  G06F13/40

Abstract: A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.

公开(公告)号：GB2505388A

公开(公告)日：2014-03-05

申请号：GB201200162

申请日：2010-09-08

Applicant: IBM

Inventor： KIRSCHT JOSEPH ALLEN ,  MCGLONE ELIZABETH ,  BLACKMON HERMAN LEE ,  HARADEN RYAN SCOTT

IPC: G06F11/14 ,  H04L1/00 ,  H04L1/18

Abstract: Systems and methods to respond to error detection are provided. A particular method may include issuing a first command to a first redrive device and a second command to a second redrive device. The method may also include reissuing the second command to the second redrive device in response to detecting a transmission error between a memory controller and the second redrive device. The method may further include storing at a first buffer first data that is received from the first redrive device in response to the first command. The method may include storing at a second buffer second data that is received from the second redrive device in response to the reissued second command. The method also may include merging the second data with the first data.

公开(公告)号：AT166733T

公开(公告)日：1998-06-15

申请号：AT95480019

申请日：1995-03-08

Applicant: IBM

Inventor： PAULSON PEDER JAMES ,  BLACKMON HERMAN LEE ,  HASELHORST KENT HAROLD ,  DREHMEL ROBERT ALLEN ,  KROLAK DAVID JOHN ,  GROSBACH LYLE EDWIN ,  MARCELLA JAMES ANTHONY

IPC: G06F13/42 ,  G06F13/40

Abstract: A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.

公开(公告)号：DE112010003684T5

公开(公告)日：2012-12-06

申请号：DE112010003684

申请日：2010-09-08

Applicant: IBM

Inventor： KIRSCHT JOSEPH ALLEN ,  BLACKMON HERMAN LEE ,  MCGLONE ELIZABETH ,  HARADEN RYAN SCOTT

IPC: G06F11/14 ,  G06F13/16

Abstract: Systeme und Verfahren zum Reagieren auf das Erkennen von Fehlern werden bereitgestellt. Ein bestimmtes Verfahren kann das Ausgeben eines ersten Befehls an eine erste Wiederansteuerungs-Einheit und eines zweiten Befehls an eine zweite Wiederansteuerungs-Einheit enthalten. Zu dem Verfahren kann auch das erneute Ausgeben des zweiten Befehls an die zweite Wiederansteuerungs-Einheit in Reaktion auf das Erkennen eines Übertragungsfehlers zwischen einer Speicher-Steuereinheit und der zweiten Wiederansteuerungs-Einheit gehören. Das Verfahren kann ferner das Speichern erster Daten, die von der ersten Wiederansteuerungs-Einheit in Reaktion auf den ersten Befehl empfangen werden, in einem ersten Puffer enthalten. Das Verfahren kann das Speichern zweiter Daten, die von der zweiten Wiederansteuerungs-Einheit in Reaktion auf den erneut ausgegebenen zweiten Befehl empfangen werden, in einem zweiten Puffer enthalten. Das Verfahren kann auch das Zusammenführen der zweiten Daten mit den ersten Daten enthalten.