公开(公告)号：WO2006095838B1

公开(公告)日：2007-03-15

申请号：PCT/JP2006304659

申请日：2006-03-02

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： CLARK SCOTT DOUGLAS ,  JOHNS CHARLES RAY ,  KROLAK DAVID JOHN ,  YAMAZAKI TAKESHI ,  BROWN JEFFREY DOUGLAS

IPC: G06F13/362

CPC classification number: G06F13/362 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151

Abstract: A data switch, a method and a computer program are provided for the transfer of data between multiple bus units in a memory system. Each bus unit is connected to a corresponding data ramp. Each data ramp is only directly connected to the adjacent data ramps. This forms at least one data ring that enables the transfer of data from each bus unit to any other bus unit in the memory system. A central arbiter manages the transfer of data between the data ramps and the transfer of data between the data ramp and its corresponding bus unit. A preferred embodiment contains four data rings, wherein two data rings transfer data clockwise and two data rings transfer data counter-clockwise.

Abstract translation: 提供数据开关，方法和计算机程序用于在存储器系统中的多个总线单元之间传送数据。 每个总线单元连接到相应的数据斜坡。 每个数据斜坡仅直接连接到相邻的数据斜坡。 这形成至少一个数据环，其使得能够将数据从每个总线单元传送到存储器系统中的任何其它总线单元。 中央仲裁器管理数据斜坡之间的数据传输和数据斜坡与其相应总线单元之间的数据传输。 优选实施例包含四个数据环，其中两个数据环顺时针传送数据，两个数据环逆时针传送数据。

公开(公告)号：WO2006095838A3

公开(公告)日：2007-02-15

申请号：PCT/JP2006304659

申请日：2006-03-02

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： CLARK SCOTT DOUGLAS ,  JOHNS CHARLES RAY ,  KROLAK DAVID JOHN ,  YAMAZAKI TAKESHI ,  BROWN JEFFREY DOUGLAS

IPC: G06F13/362

CPC classification number: G06F13/362 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151

Abstract: A data switch, a method and a computer program are provided for the transfer of data between multiple bus units in a memory system. Each bus unit is connected to a corresponding data ramp. Each data ramp is only directly connected to the adjacent data ramps. This forms at least one data ring that enables the transfer of data from each bus unit to any other bus unit in the memory system. A central arbiter manages the transfer of data between the data ramps and the transfer of data between the data ramp and its corresponding bus unit. A preferred embodiment contains four data rings, wherein two data rings transfer data clockwise and two data rings transfer data counter-clockwise.

Abstract translation: 数据交换机，方法和计算机程序被提供用于在存储器系统中的多个总线单元之间传输数据。 每个总线单元连接到相应的数据斜坡。 每个数据斜坡只直接连接到相邻的数据斜坡。 这形成至少一个数据环，该数据环能够将数据从每个总线单元传送到存储器系统中的任何其他总线单元。 中央仲裁器管理数据斜坡和数据斜坡及其相应总线单元之间的数据传输之间的数据传输。 一个优选实施例包含四个数据环，其中两个数据环顺时针传输数据，两个数据环逆时针传输数据。

公开(公告)号：DE69502656D1

公开(公告)日：1998-07-02

申请号：DE69502656

申请日：1995-03-08

Applicant: IBM

Inventor： PAULSON PEDER JAMES ,  BLACKMON HERMAN LEE ,  HASELHORST KENT HAROLD ,  DREHMEL ROBERT ALLEN ,  KROLAK DAVID JOHN ,  GROSBACH LYLE EDWIN ,  MARCELLA JAMES ANTHONY

IPC: G06F13/42 ,  G06F13/40

Abstract: A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.

公开(公告)号：AT166733T

公开(公告)日：1998-06-15

申请号：AT95480019

申请日：1995-03-08

Applicant: IBM

Inventor： PAULSON PEDER JAMES ,  BLACKMON HERMAN LEE ,  HASELHORST KENT HAROLD ,  DREHMEL ROBERT ALLEN ,  KROLAK DAVID JOHN ,  GROSBACH LYLE EDWIN ,  MARCELLA JAMES ANTHONY

IPC: G06F13/42 ,  G06F13/40

Abstract: A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.