公开(公告)号：US3065356A

公开(公告)日：1962-11-20

申请号：US10310561

申请日：1961-04-14

Applicant: IBM

Inventor： BLAKE ROBERT M ,  SHEA EDWARD T

CPC classification number: G06K7/10009

公开(公告)号：US3609692A

公开(公告)日：1971-09-28

申请号：US3609692D

申请日：1968-10-22

Applicant: IBM

Inventor： BLAKE ROBERT M ,  DINGWALL ROBERT P

IPC: G06F11/30 ,  G06F9/00 ,  G06F11/34 ,  G06F13/00 ,  H04L12/26 ,  H04L13/08 ,  H04Q5/00

CPC classification number: H04L43/00 ,  G06F11/3485 ,  G06F11/349 ,  H04L13/08 ,  H04L43/10

Abstract: A monitoring arrangement for enabling communication between a data processing system and remote users thereof in which there are included means for enabling communication between an operator and the system to permit examination of the data being sent by the system, means for enabling communication between remote users and the system to permit examination of the data being sent by the users to the system and means for alternately consecutively enabling the system information and the user information to be observed to effectively achieve bidirectional intercommunication between the system and the users. The arrangement is capable of operating in both the audio and digital modes.

公开(公告)号：CA674772A

公开(公告)日：1963-11-26

申请号：CA674772D

Applicant: IBM

Inventor： BLAKE ROBERT M

公开(公告)号：CA2002362C

公开(公告)日：1994-02-01

申请号：CA2002362

申请日：1989-11-07

Applicant: IBM

Inventor： BLAKE ROBERT M ,  BOSSEN DOUGLAS C ,  CHEN CHIN L ,  FIFIELD JOHN A ,  KALTER HOWARD L ,  LO TIN C

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/22 ,  G06F11/00

Abstract: FAULT TOLERANT COMPUTER MEMORY SYSTEMS AND COMPONENTS EMPLOYING DUAL LEVEL ERROR CORRECTION AND DETECTION WITH LOCK-UP FEATURE In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：CA2002361C

公开(公告)日：1993-12-21

申请号：CA2002361

申请日：1989-11-07

Applicant: IBM

Inventor： BLAKE ROBERT M ,  BOSSEN DOUGLAS C ,  CHEN CHIN L ,  FIFIELD JOHN A ,  KALTER HOWARD L

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/22 ,  G06F11/00

Abstract: FAULT TOLERANT COMPUTER MEMORY SYSTEMS AND COMPONENTS EMPLOYING DUAL LEVEL ERROR CORRECTION AND DETECTION WITH DISABLEMENT FEATURE In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：CA2002362A1

公开(公告)日：1990-09-10

申请号：CA2002362

申请日：1989-11-07

Applicant: IBM

Inventor： BLAKE ROBERT M ,  BOSSEN DOUGLAS C ,  CHEN CHIN L ,  FIFIELD JOHN A ,  KALTER HOWARD L ,  LO TIN C

IPC: G06F12/16 ,  G06F11/10

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：DE1207682B

公开(公告)日：1965-12-23

申请号：DEJ0021601

申请日：1962-04-12

Applicant: IBM

Inventor： BLAKE ROBERT M ,  SHEA EDWARD T

Abstract: 973,118. Sensing record cards. INTERNATIONAL BUSINESS MACHINES CORPORATION. April 4, 1962 [April 14, 1961], No. 12897/62. Heading G4M. A perforated record card is sensed columnby-column by energizing neon lamps L1-L80 in sequence, photoconductive strips PC1-PC12, one for each row of the card, providing output signals representing the recorded data and also controlling the energization of lamps L1-L80 in such a way that if any column of the card is not perforated, the next lamp in the sequence is energized after a shorter time interval than the normal decay period of strips PC1-PC12 or the normal extinction period of lamps L1-L80. Each lamp L1-L80 is provided with a lucite light guide 46 and is pulsed on by the corresponding monostable circuit D1-D80 triggered by the associated stage of a ring counter 9. A start pulse at terminal 42 pulses lamp L1, and if one or more holes are present in the first column of the card an output is obtained from OR gate 35 to trigger commutator 16 which then scans the strips PC1-PC12 to produce a differentially-timed pulse (or pulses) on lead 18. The output of OR gate 35 also inhibits gate 38 to prevent the start pulse, which has been delayed by network 32, from stepping on the ring counter 9 through OR gate 31. At the completion of a scan, commutator 16 pulses lead 17, and after a suitable delay introduced by network 34, the next lamp L2 is pulsed on. If there are no holes in a column, no output is obtained from OR gate 35, commutator 16 is not triggered and gate 38 is not inhibited, so that the pulse which initiated energization of the corresponding lamp, after passing through network 32, is recirculated and causes the next lamp to be energized. The output of strips PC1-PC12 may be taken directly from amplifiers 14, in which case commutator 16 is omitted, line 15 is connected to line 17 and delay 34 suitably adjusted to account for the decay time of the strips of the extinction time of the lamps.