公开(公告)号：CA2002362C

公开(公告)日：1994-02-01

申请号：CA2002362

申请日：1989-11-07

Applicant: IBM

Inventor： BLAKE ROBERT M ,  BOSSEN DOUGLAS C ,  CHEN CHIN L ,  FIFIELD JOHN A ,  KALTER HOWARD L ,  LO TIN C

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/22 ,  G06F11/00

Abstract: FAULT TOLERANT COMPUTER MEMORY SYSTEMS AND COMPONENTS EMPLOYING DUAL LEVEL ERROR CORRECTION AND DETECTION WITH LOCK-UP FEATURE In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：CA2002362A1

公开(公告)日：1990-09-10

申请号：CA2002362

申请日：1989-11-07

Applicant: IBM

Inventor： BLAKE ROBERT M ,  BOSSEN DOUGLAS C ,  CHEN CHIN L ,  FIFIELD JOHN A ,  KALTER HOWARD L ,  LO TIN C

IPC: G06F12/16 ,  G06F11/10

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.