公开(公告)号：CA1068410A

公开(公告)日：1979-12-18

申请号：CA272260

申请日：1977-02-21

Applicant: IBM

Inventor： CHEN CHIN L ,  RUTLEDGE ROBERT A

IPC: H04L27/18 ,  H03M13/23 ,  H04L1/00 ,  G06F11/12

Abstract: AN ERROR CORRECTION CODE AND APPARATUS FOR THE CORRECTION OF DIFFERENTIALLY ENCODED QUADRATURE PHASE SHIFT KEYED DATA (DQPSK) This specification describes a convolutional code and apparatus for the correction of errors in differentially encoded quadrature phase shift keyed data (DQPSK). In each sequence of forty bits 24 are information bits and the remainder are parity bits. Two parity bits are generated for each three information bit set in the sequence in accordance with the following equations: where i?, i? and i? are the three information bits in the set associated with the parity bits P? and p? while the other information bits are from the seven sets of the sequence preceding the set associated with the parity bits.

公开(公告)号：CA2002362C

公开(公告)日：1994-02-01

申请号：CA2002362

申请日：1989-11-07

Applicant: IBM

Inventor： BLAKE ROBERT M ,  BOSSEN DOUGLAS C ,  CHEN CHIN L ,  FIFIELD JOHN A ,  KALTER HOWARD L ,  LO TIN C

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/22 ,  G06F11/00

Abstract: FAULT TOLERANT COMPUTER MEMORY SYSTEMS AND COMPONENTS EMPLOYING DUAL LEVEL ERROR CORRECTION AND DETECTION WITH LOCK-UP FEATURE In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：CA2002361C

公开(公告)日：1993-12-21

申请号：CA2002361

申请日：1989-11-07

Applicant: IBM

Inventor： BLAKE ROBERT M ,  BOSSEN DOUGLAS C ,  CHEN CHIN L ,  FIFIELD JOHN A ,  KALTER HOWARD L

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/22 ,  G06F11/00

Abstract: FAULT TOLERANT COMPUTER MEMORY SYSTEMS AND COMPONENTS EMPLOYING DUAL LEVEL ERROR CORRECTION AND DETECTION WITH DISABLEMENT FEATURE In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：CA2013386C

公开(公告)日：1994-03-29

申请号：CA2013386

申请日：1990-03-29

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  CHEN CHIN L ,  HSIAO MU Y

IPC: G06F11/10 ,  G06K7/10 ,  G06K19/14 ,  H03M13/00 ,  H03M13/07

Abstract: METHOD AND APPARATUS FOR PROVIDING ERROR CORRECTION AND SYMBOL LEVEL CODES An error correction coding system employs a single check symbol from an arbitrary sequence of information symbols to provide single error correction at the symbol level. The sequence of information symbols may in fact also be arbitrarily long. The coding system of the present invention provides both a method and apparatus for encoding the check symbol and a method and apparatus for error correction based upon the single coded symbol character. The system is particularly applicable for use in conjunction with bar code recognition systems but is in fact applicable to a broad range of coding systems, including optical character recognition and ordinary alphanumeric codes. The system is also extendable to any system employing an odd number of code symbols that may be present in a single character position.

公开(公告)号：FR2400801A1

公开(公告)日：1979-03-16

申请号：FR7820116

申请日：1978-06-29

Applicant: IBM

Inventor： CHEN CHIN L ,  HSIAO MU Y

IPC: H03M13/00 ,  G06F11/10 ,  G11B20/18 ,  H03M13/15 ,  H03K13/32

公开(公告)号：CA2011296A1

公开(公告)日：1990-11-15

申请号：CA2011296

申请日：1990-03-01

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  CHEN CHIN L ,  DILL FREDERICK H ,  GOODMAN DOUGLAS S ,  HSIAO MU Y ,  MCCANN PAUL V ,  MULLIGAN JAMES M ,  RAND RICKY A

IPC: G06K1/12 ,  G06K7/016 ,  G06K7/10 ,  G06K19/06 ,  G06K1/00

Abstract: PRESENCE/ABSENCE BAR CODE A single width bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed The codes are also desirably dense in terms of character representations per linear centimeter, an important consideration in semiconductor manufacturing wherein space on the chips and the wafer is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences. P09-89-002

公开(公告)号：CA2002362A1

公开(公告)日：1990-09-10

申请号：CA2002362

申请日：1989-11-07

Applicant: IBM

Inventor： BLAKE ROBERT M ,  BOSSEN DOUGLAS C ,  CHEN CHIN L ,  FIFIELD JOHN A ,  KALTER HOWARD L ,  LO TIN C

IPC: G06F12/16 ,  G06F11/10

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：FR2343374A1

公开(公告)日：1977-09-30

申请号：FR7702066

申请日：1977-01-18

Applicant: IBM

Inventor： CHEN CHIN L ,  RUTLEDGE ROBERT A

IPC: H04L27/18 ,  H03M13/23 ,  H04L1/00 ,  H04L1/10

Abstract: This specification describes a convolutional code and apparatus for the correction of errors in differentially encoded quadrature phase shift keyed data (DQPSK). In each sequence of forty bits 24 are information bits and the remainder are parity bits. Two parity bits are generated for each three information bit set in the sequence in accordance with the following equations: