公开(公告)号：DE68925897D1

公开(公告)日：1996-04-11

申请号：DE68925897

申请日：1989-04-28

Applicant: IBM

Inventor： BONNEAU MARTINE ,  ONG IENG ,  GOUZE ERIC ,  PICCINO JEAN-MARC ,  HORNUNG ROBERT

IPC: H01L21/82 ,  H01L27/118

Abstract: A CMOS FET master slice integrated circuit (20) of the gate-array type implemented in a semiconductor logic chip, comprises a plurality of core cells (CELL1, CELL2, ...) arranged adjacent one another on a repetitive basis in a row direction to form horizontal stripe shaped functional gate region (21) of a determined height (H). Each core cell (e.g. CELL1) is comprised of four different sized devices: one small and one large NFET (N1.1, N2.1), thus one small and one large PFET (P1.1, P2.1), that are disposed in a column direction. The NFETs have separate gate electrodes (GN1.1, GN2.1) to define individual devices, while the PFETs have preferably a common gate electrode (GP1) to define a single device. The relative size of NFETs and PFETs have been optimized to provide the required functionality to the latches and to ensure the balanced rise and fall delays in a maximum of basic logic circuits of the chip. As a result, the use of such core cells, allows that complex logic functions, such as latches, can be implemented in gate arrays that have a density and performance comparable with standard cell circuits. In addition, the use of these core cells also permits optimization of other basic logic circuits (INV, NOR, ...) that are used in critical logic paths and clock distribution trees, where balanced delays are highly desirable.

公开(公告)号：DE3788132D1

公开(公告)日：1993-12-16

申请号：DE3788132

申请日：1987-12-01

Applicant: IBM

Inventor： BOUDON GERARD ,  ONG IENG ,  MOLLIER PIERRE

IPC: H03K19/08 ,  H03K19/013 ,  H03K19/017 ,  H03K19/0944 ,  H03K19/21 ,  H03K19/094

Abstract: A multi base 2 input Bi-CMOS NAND circuit (30) is provided wherein an output node OUT connected to an output terminal (33) is coupled between pull up (31) and pull down (32) blocks. According to the present invention, the pull up block (31) is comprised of 2 identical basic cells, each comprised of a CMOS inverter (C31, C32) driving a NPN pull up transistor (T31, T32) mounted as an emitter follower. Logic signals (A31, A32) are applied on the inputs of the inverters (C31, C32), and the inverted signal (A31, A32) is available at the emitter of the emitter follower which corresponds to the output of the cell. All emitters are tied altogether to perform an OR function and are connected to said output terminal (33). As standard, the pull down block (32) includes a logic stack (34) is comprised of 2 FETS (F31, F32) serially connected between said output node OUT and a discharge device such as a feedback NFET (Z), the gate of which is connected to said output node OUT. These 2 FETS are driving a NPN pull down transistor (T), the collector of which is also connected to the output node OUT.

公开(公告)号：DE68925897T2

公开(公告)日：1996-10-02

申请号：DE68925897

申请日：1989-04-28

Applicant: IBM

Inventor： BONNEAU MARTINE ,  ONG IENG ,  GOUZE ERIC ,  PICCINO JEAN-MARC ,  HORNUNG ROBERT

IPC: H01L21/82 ,  H01L27/118

Abstract: A CMOS FET master slice integrated circuit (20) of the gate-array type implemented in a semiconductor logic chip, comprises a plurality of core cells (CELL1, CELL2, ...) arranged adjacent one another on a repetitive basis in a row direction to form horizontal stripe shaped functional gate region (21) of a determined height (H). Each core cell (e.g. CELL1) is comprised of four different sized devices: one small and one large NFET (N1.1, N2.1), thus one small and one large PFET (P1.1, P2.1), that are disposed in a column direction. The NFETs have separate gate electrodes (GN1.1, GN2.1) to define individual devices, while the PFETs have preferably a common gate electrode (GP1) to define a single device. The relative size of NFETs and PFETs have been optimized to provide the required functionality to the latches and to ensure the balanced rise and fall delays in a maximum of basic logic circuits of the chip. As a result, the use of such core cells, allows that complex logic functions, such as latches, can be implemented in gate arrays that have a density and performance comparable with standard cell circuits. In addition, the use of these core cells also permits optimization of other basic logic circuits (INV, NOR, ...) that are used in critical logic paths and clock distribution trees, where balanced delays are highly desirable.

公开(公告)号：DE3788132T2

公开(公告)日：1994-05-11

申请号：DE3788132

申请日：1987-12-01

Applicant: IBM

Inventor： BOUDON GERARD ,  ONG IENG ,  MOLLIER PIERRE

IPC: H03K19/08 ,  H03K19/013 ,  H03K19/017 ,  H03K19/0944 ,  H03K19/21 ,  H03K19/094

Abstract: A multi base 2 input Bi-CMOS NAND circuit (30) is provided wherein an output node OUT connected to an output terminal (33) is coupled between pull up (31) and pull down (32) blocks. According to the present invention, the pull up block (31) is comprised of 2 identical basic cells, each comprised of a CMOS inverter (C31, C32) driving a NPN pull up transistor (T31, T32) mounted as an emitter follower. Logic signals (A31, A32) are applied on the inputs of the inverters (C31, C32), and the inverted signal (A31, A32) is available at the emitter of the emitter follower which corresponds to the output of the cell. All emitters are tied altogether to perform an OR function and are connected to said output terminal (33). As standard, the pull down block (32) includes a logic stack (34) is comprised of 2 FETS (F31, F32) serially connected between said output node OUT and a discharge device such as a feedback NFET (Z), the gate of which is connected to said output node OUT. These 2 FETS are driving a NPN pull down transistor (T), the collector of which is also connected to the output node OUT.

公开(公告)号：CA1313401C

公开(公告)日：1993-02-02

申请号：CA584358

申请日：1988-11-28

Applicant: IBM

Inventor： BOUDON GERARD ,  MOLLIER PIERRE ,  ONG IENG ,  AIPPERSPACH ANTHONY G ,  DANSKY ALLAN H ,  VAN PHAN NGHIA ,  PLUCHINO BIAGIO ,  ZIER STEVEN J ,  ZUCKERMAN ADRIAN

IPC: H03K19/01 ,  H03K19/094

Abstract: A MULTI-EMITTER BICMOS LOGIC CIRCUIT FAMILY WITH SUPERIOR PERFORMANCE A multi emitter multi input BICMOS NAND circuit is provided wherein an output node OUT connected to an output terminal is coupled between pull up and pull down blocks. According to one embodiment of the present invention, the pull up block is comprised of a plurality of identical basic cells, each comprised of a CMOS inverter driving an NPM pull up transistor mounted as an emitter follower. Logic signals are applied on the inputs of the inverters, and the inverted signal (A31, A32) is available at the emitter of the emitter follower which corresponds to the output of the cell. All outputs are tied altogether to perform an OR function and are connected to said output terminal to have a multi emitter like circuit. The pull down block in this embodiment is comprised of two FETs serially connected between said output node OUT and a discharge device such as a feedback NFET, the gate of which is connected to said output node OUT. These two FETs are for driving a NPM pull down transistor, the collector of which is also connected to the output node OUT. The invention includes a number of other embodiments including a feedback inverter embodiment, a parasitic node discharge embodiment, and a BIFET latch embodiment. FR9-87-016