公开(公告)号：JP2004260806A

公开(公告)日：2004-09-16

申请号：JP2004020546

申请日：2004-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BALAZICH DOUGLAS G ,  JOSEPH DOUGLAS J ,  SZWED PETER K

IPC: H04L1/00 ,  G06F12/00 ,  G06F12/04 ,  G06F13/38

CPC classification number: G06F13/387

Abstract: PROBLEM TO BE SOLVED: To eliminate necessity to perform a read operation in a read-correct-write operation. SOLUTION: A buffer and a tag which are controlled in relation to a read request, are utilized, data are transmitted and tag information is transmitted in response to these requests, to avoid the read-correct-write operation which is performed in a communication adapter. A function of this adapter is to assemble a plurality of various data blocks each having a various information quantity into a single data packet for transmitting the data packet to another memory. When an error-correcting function related to a memory of the adapter is present, utilization of the read-correct-write operation for limiting a bandwidth is required unless the present invention is utilized. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：CA2102878A1

公开(公告)日：1994-09-03

申请号：CA2102878

申请日：1993-11-10

Applicant: IBM

Inventor： FITCH BLAKE G ,  GIAMPAPA MARK E ,  JOSEPH DOUGLAS J

IPC: H04L12/56

Abstract: A message packet transmitter for transmitting a packet of electronic data signals onto a communication network without interruption. A first-in, first-out electronic memory has a transmit state in which an electronic data signal stored therein is output. The electronic memory has an idle state in which electronic data signals stored therein are not output. A message packet-in-transit identification circuit generates a packet-in-transit signal after the electronic memory outputs the first electronic data signal in a message packet. A no-packet-in-transit signal is generated after the electronic memory outputs the last electronic data signal in the message packet. A state controller maintains the electronic memory in the transmit state when the electronic memory stores at least a portion of a message packet, when the state controller receives a packet-in-transit signal, and when the state controller receives an interrupt-pending signal.

公开(公告)号：MY127786A

公开(公告)日：2006-12-29

申请号：MYPI20033059

申请日：2003-08-12

Applicant: IBM

Inventor： BOYD WILLIAM TODD ,  JOSEPH DOUGLAS J ,  KO MICHAEL ANTHONY ,  RECIO RENATO JOHN

IPC: G06F13/00 ,  G06F11/20 ,  G06F13/38 ,  H04L12/56 ,  H04L69/40

Abstract: A METHOD, COMPUTER PROGRAM PRODUCT, AND DISTRIBUTED DATA PROCESSING SYSTEM FOR SUPPORTING RNIC (RDMA ENABLED NIC) SWITCHOVER AND SWITCHBACK ARE PROVIDED. USING THE MECHANISM PROVIDED IN THE PRESENT INVENTION WHEN A PLANNED OR UNPLANNED OUTAGE OCCURS ON A PRIMARY RNIC, ALL OUTSTANDING CONNECTIONS ARE SWITCHED OVER TO AN ALTERNATE RNIC , AND THE ALTERNATE RNIC CONTINUES COMMUNICATION PROCESSING. ADDITIONALLY,USING THE MECHANISM PROVIDED IN THE PRESENT INVENTION, CONNECTIONS CAN ALSO BE SWITCHED BACK.(FIGURE 1)