公开(公告)号：GB2486378A

公开(公告)日：2012-06-13

申请号：GB201205684

申请日：2010-09-08

Applicant: IBM

Inventor： ARSOVSKI IGOR ,  BRACERAS GEORGE ,  HOULE ROBERT M ,  PILO HAROLD

IPC: G11C7/04 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22 ,  G11C11/413 ,  G11C11/419

Abstract: An SRAM delay circuit (14) that tracks bitcell characteristics. A circuit is disclosed that includes an input node for receiving an input signal (13); a reference node (20) for capturing a reference current from a plurality of reference cells (12); a capacitance network (15) having a discharge that is controlled by the reference current; and an output circuit that outputs the input signal with a delay (16), wherein the delay is controlled by the discharge of the capacitance network (15).

公开(公告)号：GB2486378B

公开(公告)日：2014-06-04

申请号：GB201205684

申请日：2010-09-08

Applicant: IBM

Inventor： ARSOVSKI IGOR ,  BRACERAS GEORGE ,  HOULE ROBERT M ,  PILO HAROLD

IPC: G11C7/04 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22 ,  G11C11/413 ,  G11C11/419

公开(公告)号：GB2486378B8

公开(公告)日：2016-03-23

申请号：GB201205684

申请日：2010-09-08

Applicant: IBM

Inventor： ARSOVSKI IGOR ,  BRACERAS GEORGE ,  HOULE ROBERT M ,  PILO HAROLD

IPC: G11C7/04 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22 ,  G11C11/413 ,  G11C11/419

公开(公告)号：GB2486378A8

公开(公告)日：2016-03-23

申请号：GB201205684

申请日：2010-09-08

Applicant: IBM

Inventor： ARSOVSKI IGOR ,  BRACERAS GEORGE ,  HOULE ROBERT M ,  PILO HAROLD

IPC: G11C7/04 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22 ,  G11C11/413 ,  G11C11/419

Abstract: An SRAM delay circuit (14) that tracks bitcell characteristics. A circuit is disclosed that includes an input node for receiving an input signal (13); a reference node (20) for capturing a reference current from a plurality of reference cells (12); a capacitance network (15) having a discharge that is controlled by the reference current; and an output circuit that outputs the input signal with a delay (16), wherein the delay is controlled by the discharge of the capacitance network (15).