公开(公告)号：IL283865D0

公开(公告)日：2021-07-29

申请号：IL28386521

申请日：2021-06-09

Applicant: IBM ,  CHRISTOPH RAISCH ,  MARCO KRAEMER ,  FRANK SIEGFRIED LEHNERT ,  MATTHIAS KLEIN ,  JONATHAN D BRADBURY ,  CHRISTIAN JACOBI ,  BRENTON BELMAR ,  PETER DANA DRIEVER

Inventor： CHRISTOPH RAISCH ,  MARCO KRAEMER ,  FRANK SIEGFRIED LEHNERT ,  MATTHIAS KLEIN ,  JONATHAN D BRADBURY ,  CHRISTIAN JACOBI ,  BRENTON BELMAR ,  PETER DANA DRIEVER

IPC: G06F9/30 ,  G06F13/16 ,  G06F13/42

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

公开(公告)号：IL284334D0

公开(公告)日：2021-08-31

申请号：IL28433421

申请日：2021-06-23

Applicant: IBM ,  CHRISTOPH RAISCH ,  MARCO KRAEMER ,  FRANK SIEGFRIED LEHNERT ,  MATTHIAS KLEIN ,  JONATHAN D BRADBURY ,  CHRISTIAN JACOBI ,  BRENTON BELMAR ,  PETER DANA DRIEVER

Inventor： CHRISTOPH RAISCH ,  MARCO KRAEMER ,  FRANK SIEGFRIED LEHNERT ,  MATTHIAS KLEIN ,  JONATHAN D BRADBURY ,  CHRISTIAN JACOBI ,  BRENTON BELMAR ,  PETER DANA DRIEVER

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/451 ,  G06F9/54 ,  G06F11/07

Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.

公开(公告)号：GB2593852B

公开(公告)日：2022-03-09

申请号：GB202111895

申请日：2020-01-16

Applicant: IBM

Inventor： CHRISTOPH RAISCH ,  MARCO KRAEMER ,  FRANK LEHNERT ,  MATTHIAS KLEIN ,  JONATHAN BRADBURY ,  CHRISTIAN JACOBI ,  BRENTON BELMAR ,  PETER DRIEVER

IPC: G06F9/312 ,  G06F9/38 ,  G06F11/07 ,  G06F11/14 ,  G06F11/30

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.