公开(公告)号：IL283865D0

公开(公告)日：2021-07-29

申请号：IL28386521

申请日：2021-06-09

Applicant: IBM ,  CHRISTOPH RAISCH ,  MARCO KRAEMER ,  FRANK SIEGFRIED LEHNERT ,  MATTHIAS KLEIN ,  JONATHAN D BRADBURY ,  CHRISTIAN JACOBI ,  BRENTON BELMAR ,  PETER DANA DRIEVER

Inventor： CHRISTOPH RAISCH ,  MARCO KRAEMER ,  FRANK SIEGFRIED LEHNERT ,  MATTHIAS KLEIN ,  JONATHAN D BRADBURY ,  CHRISTIAN JACOBI ,  BRENTON BELMAR ,  PETER DANA DRIEVER

IPC: G06F9/30 ,  G06F13/16 ,  G06F13/42

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

公开(公告)号：IL284334D0

公开(公告)日：2021-08-31

申请号：IL28433421

申请日：2021-06-23

Applicant: IBM ,  CHRISTOPH RAISCH ,  MARCO KRAEMER ,  FRANK SIEGFRIED LEHNERT ,  MATTHIAS KLEIN ,  JONATHAN D BRADBURY ,  CHRISTIAN JACOBI ,  BRENTON BELMAR ,  PETER DANA DRIEVER

Inventor： CHRISTOPH RAISCH ,  MARCO KRAEMER ,  FRANK SIEGFRIED LEHNERT ,  MATTHIAS KLEIN ,  JONATHAN D BRADBURY ,  CHRISTIAN JACOBI ,  BRENTON BELMAR ,  PETER DANA DRIEVER

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/451 ,  G06F9/54 ,  G06F11/07

Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.

公开(公告)号：GB2532640B

公开(公告)日：2018-04-04

申请号：GB201602460

申请日：2014-06-23

Applicant: IBM

Inventor： HENRY JOSEPH MAY ,  ROGER HATHORN ,  PATRICIA DRIEVER ,  CHRISTOPH RAISCH ,  DANIEL SENTLER

IPC: H04L12/931 ,  H04L12/911 ,  H04L12/939

公开(公告)号：IL284681D0

公开(公告)日：2021-08-31

申请号：IL28468121

申请日：2021-07-07

Applicant: IBM ,  MARCO KRAEMER ,  CHRISTOPH RAISCH ,  BERND NERZ ,  DONALD W SCHMIDT ,  MATTHIAS KLEIN ,  SASCHA JUNGHANS ,  PETER DANA DRIEVER

Inventor： MARCO KRAEMER ,  CHRISTOPH RAISCH ,  BERND NERZ ,  DONALD W SCHMIDT ,  MATTHIAS KLEIN ,  SASCHA JUNGHANS ,  PETER DANA DRIEVER

IPC: G06F9/455 ,  G06F9/48 ,  G06F9/54 ,  G06F13/24

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

公开(公告)号：GB2532640A

公开(公告)日：2016-05-25

申请号：GB201602460

申请日：2014-06-23

Applicant: IBM

Inventor： HENRY JOSEPH MAY ,  ROGER HATHORN ,  PATRICIA DRIEVER ,  CHRISTOPH RAISCH ,  DANIEL SENTLER

IPC: H04L12/931 ,  H04L12/911 ,  H04L12/939

Abstract: Provided are a method, a system, and a computer program product in which a plurality of switches are maintained in a cascaded configuration. A switch relays a switch fabric internal link services (SW-ILS) to generate a pair of exchanges comprising a first exchange and a second exchange at the switch. In response to a termination of the first exchange of the pair of exchanges, the second exchange of the pair of exchanges is terminated.

公开(公告)号：GB2593852B

公开(公告)日：2022-03-09

申请号：GB202111895

申请日：2020-01-16

Applicant: IBM

Inventor： CHRISTOPH RAISCH ,  MARCO KRAEMER ,  FRANK LEHNERT ,  MATTHIAS KLEIN ,  JONATHAN BRADBURY ,  CHRISTIAN JACOBI ,  BRENTON BELMAR ,  PETER DRIEVER

IPC: G06F9/312 ,  G06F9/38 ,  G06F11/07 ,  G06F11/14 ,  G06F11/30

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.

公开(公告)号：GB2502743B

公开(公告)日：2018-06-27

申请号：GB201316176

申请日：2012-02-28

Applicant: IBM

Inventor： CLAUDE BASSO ,  DANIEL EISENHAUER ,  WILLIAM ARMSTRONG ,  RENATO RECIO ,  HENRY JOSEPH MAY ,  CHRISTOPH RAISCH ,  JOSEP CORS ,  CHIH-JEN CHANG ,  COLIN VERRILLI ,  CHETAN YALIWAL

IPC: H04L45/74 ,  H04L45/50

Abstract: A network node that forwards traffic of a converged network received from a source end node receives a second message addressed to the network node, but intended for the source end node. The second message includes at least a portion of a first message originated by the source end node and previously forwarded by the network node. The network node extracts from the first message a source identifier of the source end node in a first communication protocol and determines by reference to a data structure a destination address of the second message in a second communication protocol. The network node modifies the second message to include the destination address and forwards the second message toward the source end node in accordance with the destination address.