公开(公告)号：GB2604085B

公开(公告)日：2022-12-07

申请号：GB202209153

申请日：2020-11-19

Applicant: IBM

Inventor： HUNG QUI LE ,  BRIAN DAVID BARRICK ,  SUSAN EISEN ,  DUNG QUOC NGUYEN ,  ANDREAS WAGNER ,  BRIAN WILLIAM THOMPTO ,  KENNETH WARD ,  STEVEN BATTLE

IPC: G06F9/38 ,  G06F9/30 ,  G06F17/16

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one processor having a main register file, the main register file having a plurality of entries for storing data; one or more execution units including a dense math execution unit; and at least one accumulator register file, the at least one accumulator register file associated with the dense math execution unit. The processor in an embodiment is configured to process data in the dense math execution unit where the results of the dense math execution unit are written to a first group of one or more accumulator register file entries, and after a checkpoint boundary is crossed based upon, for example, the number “N” of instructions dispatched after the start of the checkpoint, the results of the dense math execution unit are written to a second group of one or more accumulator register file entries.

公开(公告)号：GB2604085A

公开(公告)日：2022-08-24

申请号：GB202209153

申请日：2020-11-19

Applicant: IBM

Inventor： HUNG QUI LE ,  BRIAN DAVID BARRICK ,  SUSAN EISEN ,  DUNG QUOC NGUYEN ,  ANDREAS WAGNER ,  BRIAN WILLIAM THOMPTO ,  KENNETH WARD ,  STEVEN BATTLE

IPC: G06F9/30 ,  G06F9/38 ,  G06F17/16

Abstract: A computer system, processor (110), and method for processing information is disclosed that includes at least one processor (110) having a main register file (380), the main register file (380) having a plurality of entries (381) for storing data; one or more execution units including a dense math execution unit (460); and at least one accumulator register file (470), the at least one accumulator register file (470) associated with the dense math execution unit (460). The processor (110) in an embodiment is configured to process data in the dense math execution unit (460) where the results of the dense math execution unit (460) are written to a first group of one or more accumulator register file entries (471), and after a checkpoint boundary is crossed based upon, for example, the number "N" of instructions dispatched after the start of the checkpoint, the results of the dense math execution unit (460) are written to a second group of one or more accumulator register file entries (471).

公开(公告)号：GB2574171B

公开(公告)日：2020-04-22

申请号：GB201914312

申请日：2018-02-27

Applicant: IBM

Inventor： GREGORY WILLIAM ALEXANDER ,  SOMIN SONG ,  BRIAN DAVID BARRICK ,  ANTHONY SAPORITO ,  CHRISTIAN JACOBI ,  AARON TSAI ,  THOMAS WINTERS FOX

IPC: G06F9/38 ,  G06F12/0811

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

公开(公告)号：GB2574171A8

公开(公告)日：2019-12-04

申请号：GB201914312

申请日：2018-02-27

Applicant: IBM

Inventor： GREGORY WILLIAM ALEXANDER ,  SOMIN SONG ,  BRIAN DAVID BARRICK ,  ANTHONY SAPORITO ,  CHRISTIAN JACOBI ,  AARON TSAI ,  THOMAS WINTERS FOX

IPC: G06F9/38 ,  G06F12/0811

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

公开(公告)号：GB2574171A

公开(公告)日：2019-11-27

申请号：GB201914312

申请日：2018-02-27

Applicant: IBM

Inventor： GREGORY WILLIAM ALEXANDER ,  SOMIN SONG ,  BRIAN DAVID BARRICK ,  ANTHONY SAPORITO ,  CHRISTIAN JACOBI ,  AARON TSAI ,  THOMAS WINTERS FOX

IPC: G06F9/38 ,  G06F12/0811

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.