公开(公告)号：GB2486155B

公开(公告)日：2017-04-19

申请号：GB201206367

申请日：2010-12-13

Applicant: IBM

Inventor： CHRISTIAN JACOBI ,  BRIAN WILLIAM THOMPTO ,  GREGORY WILLIAM ALEXANDER ,  KHARY JASON ALEXANDER ,  BRIAN WILLIAM CURRAN ,  JAMES RUSSELL MITCHELL ,  JONATHAN TING HSIEH ,  BRIAN ROBERT PRASKY

IPC: G06F9/38

公开(公告)号：GB2574171B

公开(公告)日：2020-04-22

申请号：GB201914312

申请日：2018-02-27

Applicant: IBM

Inventor： GREGORY WILLIAM ALEXANDER ,  SOMIN SONG ,  BRIAN DAVID BARRICK ,  ANTHONY SAPORITO ,  CHRISTIAN JACOBI ,  AARON TSAI ,  THOMAS WINTERS FOX

IPC: G06F9/38 ,  G06F12/0811

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

公开(公告)号：GB2574171A8

公开(公告)日：2019-12-04

申请号：GB201914312

申请日：2018-02-27

Applicant: IBM

Inventor： GREGORY WILLIAM ALEXANDER ,  SOMIN SONG ,  BRIAN DAVID BARRICK ,  ANTHONY SAPORITO ,  CHRISTIAN JACOBI ,  AARON TSAI ,  THOMAS WINTERS FOX

IPC: G06F9/38 ,  G06F12/0811

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

公开(公告)号：GB2574171A

公开(公告)日：2019-11-27

申请号：GB201914312

申请日：2018-02-27

Applicant: IBM

Inventor： GREGORY WILLIAM ALEXANDER ,  SOMIN SONG ,  BRIAN DAVID BARRICK ,  ANTHONY SAPORITO ,  CHRISTIAN JACOBI ,  AARON TSAI ,  THOMAS WINTERS FOX

IPC: G06F9/38 ,  G06F12/0811

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.