1.
    发明专利
    未知

    公开(公告)号:DE69009474D1

    公开(公告)日:1994-07-07

    申请号:DE69009474

    申请日:1990-09-14

    Applicant: IBM

    Abstract: A method of passivating etched mirror facets of semiconductor laser diodes for enhancing device reliability. The etched mirror facet is first subjected to a wet-etch process to substantially remove any native oxide as well as any surface layer which may have been mechanically damaged during the preceding mirror etch process. Then, a passivation pre-treatment is applied whereby any residual oxygen is removed and a sub-monolayer is formed which permanently reduces the non-radiative recombination of minority carriers at the mirror facet. Finally, the pre-treated mirror surface is coated with a passivation layer to avoid any environmental effect on the mirror.

    2.
    发明专利
    未知

    公开(公告)号:DE69009474T2

    公开(公告)日:1994-12-01

    申请号:DE69009474

    申请日:1990-09-14

    Applicant: IBM

    Abstract: A method of passivating etched mirror facets of semiconductor laser diodes for enhancing device reliability. The etched mirror facet is first subjected to a wet-etch process to substantially remove any native oxide as well as any surface layer which may have been mechanically damaged during the preceding mirror etch process. Then, a passivation pre-treatment is applied whereby any residual oxygen is removed and a sub-monolayer is formed which permanently reduces the non-radiative recombination of minority carriers at the mirror facet. Finally, the pre-treated mirror surface is coated with a passivation layer to avoid any environmental effect on the mirror.

    Clock recovery method and apparatus

    公开(公告)号:GB2520716A

    公开(公告)日:2015-06-03

    申请号:GB201321031

    申请日:2013-11-28

    Applicant: IBM

    Abstract: Disclosed is a clock recovery method for a data receiving unit (1, fig.1). The data receiver may comprise sampling latches (2, fig.1), a multiphase generator (3, fig.1), and a clock recovery unit (5, fig.1) controlling a phase rotation unit (4, fig 1). The method, which may be carried out in the clock recovery unit (5, fig.1), comprises the steps of: obtaining an early/late signal E/L from an incoming data stream DI, wherein the early/late signal indicates if a set of one or more data samples of the incoming data stream DI is earlier or later than an edge of a clock signal phase-rotated by an amount depending on a phase offset value PR; updating a phase rotation counter value phtot in response to the early/late signal; and providing the phase offset value PR depending on a rounded phase rotation counter value phtot; wherein the phase offset value PR is determined by a look-ahead function 19, 20 which maintains, increments or decrements the rounded phase rotation counter value phtot depending on the early/late signal E/L and on the phase rotation counter value phtot. The system reduces latency and jitter.

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