公开(公告)号：DE19944359C2

公开(公告)日：2003-03-27

申请号：DE19944359

申请日：1999-09-16

Applicant: IBM DEUTSCHLAND

Inventor： BUECHNER THOMAS ,  FRITZ ROLF ,  HELMS MARKUS ,  LAMB KIRK ,  SCHLIPF THOMAS ,  WALZ MANFRED

IPC: G06F11/30

公开(公告)号：DE19944359A1

公开(公告)日：2000-05-04

申请号：DE19944359

申请日：1999-09-16

Applicant: IBM DEUTSCHLAND

Inventor： BUECHNER THOMAS ,  FRITZ ROLF ,  HELMS MARKUS ,  LAMB KIRK ,  SCHLIPF THOMAS ,  WALZ MANFRED

IPC: G06F11/30

Abstract: The method involves storing data relating to the operation path in a memory (15), the operation path containing a description of a sequence of operations. A unique operation ID is assigned to each operation. The ID remains constant during the processing of the operation by a number of functional units of the computer system to be monitored. An operation is assigned to an associated operation graph (14) containing status control data for the functional units, and the contents of the memory are evaluated to obtain tracking data. A computer system is also claimed.

公开(公告)号：GB2456618A

公开(公告)日：2009-07-22

申请号：GB0822285

申请日：2008-12-08

Applicant: IBM

Inventor： KOENIG ANDREAS ,  KLEIN MATTHIAS ,  WALZ MANFRED ,  BUECHNER THOMAS

IPC: G06F11/07

Abstract: Disclosed is a method and circuit for operating self-checking logic 16, 18, 28 in a computer processing chip 10. The chip has functional units for detecting errors 28, for tracing the errors 18, and for controlling the processor clock 16, such that a clock-stop signal is generated by the self-checking logic which is used for error management and recovery. When a stop-clock signal is generated the signal is intercepted 440, a delay 445 is defined during which error-related, chip internal error handling and/ or recovery preparation actions are processed 470. At the end of the predetermined delay 460 the clock-stop action is performed 490, 495. A warning message to firmware may be sent to help in error and recovery management. The delay may be configured according to the location of the failure, the time needed to communicate with the stop-clock signal to the clock mechanism on the chip and/or the time needed to collect and store debug data.