公开(公告)号：CA1156767A

公开(公告)日：1983-11-08

申请号：CA364528

申请日：1980-11-12

Applicant: IBM

Inventor： BURK JOHN L ,  CORMIER ROGER L ,  HARTUNG MICHAEL H ,  LARNER RAY A ,  LUCAS DONALD J ,  LYNCH KENNETH R ,  MOORE BRIAN B ,  PAGE HOWARD L ,  WANSOR DAVID H ,  ZEITLER CARL JR

IPC: G06F13/00 ,  G06F13/12 ,  G06F15/167 ,  G06F9/00 ,  G06F15/00

Abstract: Secondary storage subsystems exchange messages and data with host data processing systems and also forward messages between host systems. Host systems thereby communicate with each other in addition to having access to data in subsystem storage. Access to subsystem storage is initiated by a "request" sent from a host to the subsystem. Each request is a message containing an array of one or more commands, each command specifying a transfer of data or a control function to be performed by the subsystem. A subsystem may process more than one request at a time. It also may process the commands in a request in an arbitrary sequence suited to the availability of subsystem resources and data links to host systems. After all commands in a request have been processed the subsystem transmits an associated "completion" message to the host system which originated the request. The completion message indicates the status of completion or abnormal termination of each command in the associated request. An "adapter" processor associated with each host and subsystem operates on an asynchronous basis to transfer messages and data relative to the associated host or subsystem. One or more processing "engines" in each adapter communicates with one or more CPU's in the associated host or subsystem through an associated "adapter store". A portion of each adapter store is used as a buffer pool for constructing "subchannel control spaces" to control transfers of messages and data. Elements of each subchannel control space are returned to free status as soon as they are not needed for sustaining associated transfers. PO9-78-012

公开(公告)号：CA1180464A

公开(公告)日：1985-01-02

申请号：CA417965

申请日：1982-12-17

Applicant: IBM

Inventor： BURK JOHN L ,  BUTWELL JUSTIN R ,  CLARK CARL E ,  RODELL JOHN T ,  STUCKI DAVID E

IPC: G06F12/14 ,  G06F13/00

Abstract: STORAGE FETCH PROTECT OVERRIDE CONTROLS This invention relates to the fetch protection of a critical area in the main storage (MS) of a data processing system. The critical area is smaller than, and contained within, the size of a main storage block protectable by a single storage protect key having a fetch protection field. This invention extends protect key operations for system/370 extended architectures that use 4KB pages. This invention recognizes that system integrity is enhanced by providing different types of fetch protection within the PSA page which cannot be done with the associated 4KB key. To enable different fetch protections within a special 4KB block, this invention provides fetch protect override controls to partly override the normal operation of the 4KB storage key for a page located at a predetermined real address in MS. While 4KB fetch protection is set on for the special page's 4KB block, the fetch protect override controls disable fetch protection for a portion of the special page's real addresses (e.g. addresses 0-2047). Override enablement is controlled by a fetch protect override control bit in a control register (e.g. bit 6 of control register 0).

公开(公告)号：CA989521A

公开(公告)日：1976-05-18

申请号：CA174806

申请日：1973-06-22

Applicant: IBM

Inventor： BURK JOHN L ,  HOGAN SPURGEON G JR ,  LARSON RUSSELL H ,  MCGILVRAY BRUCE L

IPC: G06F12/08 ,  G06F12/10

Abstract: This specification describes a virtual memory system comprising a main storage and a smaller high speed buffer. Both main storage and the buffer are real-address oriented. Current virtual-to-real address translations are retained in a Translation Look Aside Table (TLAT) and real addresses of data stored in the buffer are maintained in a buffer directory. The CPU-provided virtual address causes access to the TLAT and to the buffer directory. The virtual address stored in the word accessed from the TLAT is compared to the virtual address from the CPU and the real addresses accessed from the TLAT and the buffer directory are compared to each other. If both comparisons are equal, the data is accessed from the buffer.