公开(公告)号：FR2357006A1

公开(公告)日：1978-01-27

申请号：FR7716055

申请日：1977-05-18

Applicant: IBM

Inventor： CALLAHAN ROBERT W ,  KAUFFMAN PAUL E ,  KOBESKY LAWRENCE J ,  PAGE HOWARD L

IPC: G06F13/12 ,  G06F13/00 ,  G06F9/18

公开(公告)号：CA1156767A

公开(公告)日：1983-11-08

申请号：CA364528

申请日：1980-11-12

Applicant: IBM

Inventor： BURK JOHN L ,  CORMIER ROGER L ,  HARTUNG MICHAEL H ,  LARNER RAY A ,  LUCAS DONALD J ,  LYNCH KENNETH R ,  MOORE BRIAN B ,  PAGE HOWARD L ,  WANSOR DAVID H ,  ZEITLER CARL JR

IPC: G06F13/00 ,  G06F13/12 ,  G06F15/167 ,  G06F9/00 ,  G06F15/00

Abstract: Secondary storage subsystems exchange messages and data with host data processing systems and also forward messages between host systems. Host systems thereby communicate with each other in addition to having access to data in subsystem storage. Access to subsystem storage is initiated by a "request" sent from a host to the subsystem. Each request is a message containing an array of one or more commands, each command specifying a transfer of data or a control function to be performed by the subsystem. A subsystem may process more than one request at a time. It also may process the commands in a request in an arbitrary sequence suited to the availability of subsystem resources and data links to host systems. After all commands in a request have been processed the subsystem transmits an associated "completion" message to the host system which originated the request. The completion message indicates the status of completion or abnormal termination of each command in the associated request. An "adapter" processor associated with each host and subsystem operates on an asynchronous basis to transfer messages and data relative to the associated host or subsystem. One or more processing "engines" in each adapter communicates with one or more CPU's in the associated host or subsystem through an associated "adapter store". A portion of each adapter store is used as a buffer pool for constructing "subchannel control spaces" to control transfers of messages and data. Elements of each subchannel control space are returned to free status as soon as they are not needed for sustaining associated transfers. PO9-78-012

公开(公告)号：FR2399065A1

公开(公告)日：1979-02-23

申请号：FR7819408

申请日：1978-06-20

Applicant: IBM

Inventor： MITCHELL MATTHEW J JR ,  PAGE HOWARD L

IPC: G06F13/12 ,  G06F13/38 ,  G06F15/17 ,  G06F13/00

Abstract: A high performance channel-to-channel adapter for interconnecting two or more digital computers or digital data processors. Multiple input/output device addresses are recognized by the channel-to-channel adapter. The channel-to-channel adapter makes the proper processor-to-processor connection by matching device addresses. In particular, it interconnects for data transfer purposes the two processors for which the same device address has been received. The assignment of device addresses for processor use and the direction of data transfer are by conventions agreed to among the software systems executing on the interconnected processors. The channel-to-channel adapter does not have a view of these conventions. In the more general case, two device addresses are assigned by software convention to each processor-to-processor link, one address being used to transfer data in one direction and the other address being used to transfer data in the opposite direction.

公开(公告)号：CA1172375A

公开(公告)日：1984-08-07

申请号：CA409384

申请日：1982-08-13

Applicant: IBM

Inventor： PAGE HOWARD L ,  WINGERT JAMES A

IPC: G06F9/40 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/45 ,  G06F9/50 ,  G06F12/02 ,  G06F9/46 ,  G11C9/06

Abstract: A computer architecture is disclosed which permits intersegment program calls with associated selective allocation of data segments of varying lengths. The calling program controls selective allocation of segments to the called program but the called program controls the lengths of the segments being allocated. In this way, recursive calls to the same program cannot affect the function or data of other programs or of the same program in a previous call. Also allocation of data segments can be postponed until execution resulting in more flexible execution of programs written without knowledge of the details of other co-executing programs.

公开(公告)号：CA1097821A

公开(公告)日：1981-03-17

申请号：CA301809

申请日：1978-04-24

Applicant: IBM

Inventor： MITCHELL MATTHEW J JR ,  PAGE HOWARD L

IPC: G06F13/12 ,  G06F13/38 ,  G06F15/17 ,  G06F3/04

Abstract: SYNCHRONIZING CHANNEL-TO-CHANNEL ADAPTER A high performance channel-to-channel adapter for interconnecting two or more digital computers or digital data processors. Multiple input/output device addresses are recognized by the channel-to-channel adapter. The channel-to-channel adapter makes the proper processorto-processor connection by matching device addresses. In particular, it interconnects for data transfer purposes the two processors for which the same device address has been received. The assignment of device addresses for processor use and the direction of data transfer are by conventions agreed to among the software systems executing on the interconnected processors. The channel-to-channel adapter does not have a view of these conventions. In the more general case, two device addresses are assigned by software convention to each processor-to-processor link, one address being used to transfer data in one direction and the other address being used to transfer data in the opposite direction.