公开(公告)号：US3801836A

公开(公告)日：1974-04-02

申请号：US3801836D

申请日：1972-01-07

Applicant: IBM

Inventor： CASTRUCCI P ,  GROCHOWSKI E ,  NORTH W ,  PALFI T

IPC: F16N27/00 ,  H01L21/761 ,  H01L23/535 ,  H01L27/00 ,  H01L27/102 ,  H01L29/417 ,  H01L19/00

CPC classification number: H01L29/41708 ,  F16N27/00 ,  H01L21/761 ,  H01L23/535 ,  H01L27/00 ,  H01L27/1025 ,  H01L2924/0002 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/151 ,  H01L2924/00

Abstract: A planar integrated semiconductor circuit having common emitter transistor elements isolated from each other and from other transistors by the emitter regions which form a PN or rectifying junction with the body of the semiconductor member in which the integrated circuit is formed. In a semiconductor member or body of one type conductivity, a plurality of emitter regions of opposite type conductivity extend from one planar surface of the body. One or more of the emitter regions each have a plurality of discrete base regions of the one type conductivity extending from said planar surface fully enclosed within the emitter region. Each of the base regions in turn has at least one collector region enclosed within it at the planar surface. The emitter region has a higher majority carrier concentration than the majority carrier concentration within its enclosed base regions. The rectifying junction formed by the opposite conductivity emitter region with the one type conductivity semiconductor body serves to isolate the emitter regions from each other.

Abstract translation: 一种平面集成半导体电路，具有通过与其中形成集成电路的半导体部件的主体形成PN或整流的发射极区彼此隔离并与其它晶体管隔离的共同发射极晶体管元件。 在一种导电类型的半导体部件或本体中，具有相反导电性的多个发射极区从主体的一个平面延伸。 一个或多个发射极区域各自具有从完全封装在发射极区域内的所述平坦表面延伸的一种类型电导率的多个离散基极区域。 每个基本区域依次具有在平坦表面处封装在其内的至少一个收集器区域。 发射极区域具有比其封闭的基极区域内的多数载流子浓度更高的载流子浓度。 由相反的导电性发射极区域与一个导电型半导体体形成的整流用于隔离发射极区域。

公开(公告)号：SE323436B

公开(公告)日：1970-05-04

申请号：SE832367

申请日：1967-06-13

Applicant: IBM

Inventor： PALFI T ,  BUTLER J ,  IM S

IPC: H01L23/473 ,  H05K7/20

Abstract: 1,178,566. Circuit assemblies. INTERNATIONAL BUSINESS MACHINES CORP. 27 April, 1967 [13 June, 1966], No. 19418/67. Heading H1R. In a circuit module in which the electronic circuit devices are each positioned in an aperture of a first circuit board and are interconnected with this board and a second circuit board positioned adjacent one face of the first board, the devices are cooled by means positioned adjacent the other face of the first board. As shown in the opened-out arrangement of Fig. 1A a metal cooling plate 16 is provided with a plurality of pedestals 20 each of which supports a monolithic circuit chip 22, 24 and each pedestal and its associated chip nest within an aperture in multilayer printed circuit board 18 so that the upper face of the chip 22 is coplanar with the upper face of circuit board 18. Recessed contact sockets 30, 32, 34 are disposed on the surface of board 18 and are interconnected with chip 22 via signal conductors 36. A plurality of shorter interconnecting conductors 38 provide power interconnections between the various conducting layers of circuit board 18 and chip 22, Fig. 2 (not shown). Recessed contact sockets 40 disposed about the edge of board 18 mate with power studs 50 of lower board 14 which comprises a multilayer circuit board 42, a stiffener plate 44 and a plurality of interconnecting pins 46. Board 42 has two signal interconnection layers 52, 54 with conductor lines running in the X- direction on layer 52 and in the Y-direction on layer 54 and a grounded shielding plane 56. Signal interconnections between the chips are provided through multilayer circuit board 42 which board has its circuits interconnected by through hole connections and connected to sockets 30, 32 &c. on board 18 by studs 48. A plurality of the modules 10 are plugged into a multilayer circuit board, Fig. 3 (not shown), and has a water-cooling manifold fitted directly over the modules so that the coolant fluid flows over the tops of cooling plates mounted on plates 16 and carries the heat away. The printed circuit board 18 includes an insulating layer having a high dielectric constant and board 14 includes an insulating layer having a low dielectric constant.