公开(公告)号：SE317134B

公开(公告)日：1969-11-10

申请号：SE1001464

申请日：1964-08-19

Applicant: IBM

Inventor： IM S

IPC: C23C10/22 ,  C30B31/02 ,  H01L21/00 ,  H01L23/29 ,  H01L23/482 ,  H01L29/00 ,  H01L7/46

Abstract: 1,053,105. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 18, 1964 [Aug. 19, 1963], No. 33635/64. Heading H1K. A plurality of PN junction devices are simultaneously manufactured by coating selected areas of a semi -conductor wafer of one conductivity type with metal, immersing the coated wafer in a melt saturated with said metal and containing also dopant characteristic of the opposite conductivity type, withdrawing the wafer with dopant combining material adhering to the coated areas, cooling, and then heating to form alloy junctions beneath the films. In a typical case pairs of holes 12, 13 (Fig. 3) are formed by photo-engraving in a film consisting of silicon oxide overlaid with glass (the method of making which is described) on a degenerate P-type germanium or gallium arsenide wafer. Gold, silver or, with germanium, copper is vapour deposited into the holes through an apertured molybdenum mask. After dipping in solder flux the wafer is slowly heated to 200‹ C. and then plunged into the melt. This contains a solid lump of the vapour deposited metal and consists of arsenic and tin, or arsenic, lead and tin if the wafer is germanium or of tin, tin-gold alloy, or indium or gold doped with tin, sulphur, selenium or tellurium if the wafer is gallium arsenide. After withdrawal from the melt and cooling, the wafer is reheated to 500-600‹ C. to form PN junctions beneath the holes. The metal residues are then etched away and replaced by evaporated gold contacts. which for use with germanium are doped with antimony. After annealing at 400‹ C. to reduce the peak currents of the resulting tunnel diodes the wafer is split into devices each containing one small and one large junction. The devices which may then be further annealed are used with the small junction forward biased.

公开(公告)号：SE323436B

公开(公告)日：1970-05-04

申请号：SE832367

申请日：1967-06-13

Applicant: IBM

Inventor： PALFI T ,  BUTLER J ,  IM S

IPC: H01L23/473 ,  H05K7/20

Abstract: 1,178,566. Circuit assemblies. INTERNATIONAL BUSINESS MACHINES CORP. 27 April, 1967 [13 June, 1966], No. 19418/67. Heading H1R. In a circuit module in which the electronic circuit devices are each positioned in an aperture of a first circuit board and are interconnected with this board and a second circuit board positioned adjacent one face of the first board, the devices are cooled by means positioned adjacent the other face of the first board. As shown in the opened-out arrangement of Fig. 1A a metal cooling plate 16 is provided with a plurality of pedestals 20 each of which supports a monolithic circuit chip 22, 24 and each pedestal and its associated chip nest within an aperture in multilayer printed circuit board 18 so that the upper face of the chip 22 is coplanar with the upper face of circuit board 18. Recessed contact sockets 30, 32, 34 are disposed on the surface of board 18 and are interconnected with chip 22 via signal conductors 36. A plurality of shorter interconnecting conductors 38 provide power interconnections between the various conducting layers of circuit board 18 and chip 22, Fig. 2 (not shown). Recessed contact sockets 40 disposed about the edge of board 18 mate with power studs 50 of lower board 14 which comprises a multilayer circuit board 42, a stiffener plate 44 and a plurality of interconnecting pins 46. Board 42 has two signal interconnection layers 52, 54 with conductor lines running in the X- direction on layer 52 and in the Y-direction on layer 54 and a grounded shielding plane 56. Signal interconnections between the chips are provided through multilayer circuit board 42 which board has its circuits interconnected by through hole connections and connected to sockets 30, 32 &c. on board 18 by studs 48. A plurality of the modules 10 are plugged into a multilayer circuit board, Fig. 3 (not shown), and has a water-cooling manifold fitted directly over the modules so that the coolant fluid flows over the tops of cooling plates mounted on plates 16 and carries the heat away. The printed circuit board 18 includes an insulating layer having a high dielectric constant and board 14 includes an insulating layer having a low dielectric constant.

公开(公告)号：SE345343B

公开(公告)日：1972-05-23

申请号：SE312367

申请日：1967-03-07

Applicant: IBM

Inventor： CHANCE D ,  IM S ,  PERRI J ,  RISEMAN J

IPC: B23K1/005 ,  H01L29/12 ,  H01R12/71 ,  H01L1/14

Abstract: 1,162,184. Semi-conductor devices; printed circuit assemblies. INTERNATIONAL BUSINESS MACHINES CORP. 9 March, 1967, No. 11043/67. Headings H1K and H1R. Monolithic or integrated semi-conductor devices are gold-coated on their lower surfaces and hot pressure bonded to superposed gold and chromium layers at the bottom of cavities in a substrate of glass or ceramic (e.g. 96% alumina). The cavities are formed by pressing the green ceramic or by bonding an apertured alumina sheet to an alumina blank. Each device has a plurality of built-up contacts extending through a protective glass coating on its upper surface and these lie in substantially the same plane as lands on the top surface of the substrate and which consist of aluminium, copper, or one or more noble metals. (For example the lands may have superposed gold, copper, and chromium layers). A plate is provided with conductive tracks suitably placed to interconnect adjacent contacts and lands. Suitable plates are aluminium or copper foils, paper, resin-reinforced fibrous materials, tetrafluoroethylene resins, polyethylene-terephthalate resins, and polyimide resins. The conductive tracks are formed on these, preferably on an intermediate acrylate resin parting layer, by laminating and etching, or by masked evaporation and may consist of aluminium, copper, or one or more noble metals. (A track may have superposed gold, lead, tin and copper layers). Preferably the plate is transparent so that visual alignment may be used in the bonding process, and is preferably insulating so that interconnection tests may be made before bonding. The backing may be clamped to the devices and substrate on a hot stage (which may have orienting pegs engaging the backing) and the assembly bonded by a solder reflow technique using lead-tin solder. Instead, single or multi-tipped thermocompression bonding machines may be used, the tips penetrating the backing during bonding. If ultrasonic bonding heads are used these are first heated to penetrate the backing and ultrasonic energy then supplied to affect the bonding. Laser or electron beam bonding may be used instead. The bonding layer is pulled away from the bonded contact tracks and lands, any parting layer being dissolved away. Alternatively the backing plate may be multilayered and consist of polyimide sheets bearing conductive tracks formed by masked evaporation or electrochemical deposition. Through-holes in the backing are metallized to provide interconnection between tracks in the various planes. Such a backing plate remains in place after bonding to interconnect the devices on the substrate.