公开(公告)号：JP2000112910A

公开(公告)日：2000-04-21

申请号：JP18183999

申请日：1999-06-28

Applicant: IBM

Inventor： CARPENTER GARY D ,  MARK EDWARD DEAN ,  DAVID BRIAN GLASCO ,  RICHARD NICHOLAS ACHETTA JR

IPC: G06F15/177 ,  G06F12/08 ,  G06F13/38 ,  G06F15/17

Abstract: PROBLEM TO BE SOLVED: To provide a nonuniform memory access(NUMA) computer system having a short inter-node communication waiting duration by providing a buffer control logic or the like for extracting a specified communication transaction from a transaction buffer and processing it by a third processing node. SOLUTION: This NUMA computer system 8 is provided with the transaction buffer connected to a mutual connecting means. This transaction buffer stores a communication transaction which defines the processing node excepting for a third processing node 10c as the destination (target). Corresponding to the determination to process the specified communication transaction, which originally defines the other processing node as the destination, by the third processing node 10c, the buffer control logic connected to the transaction buffer extracts the specified communication transaction from the transaction buffer and the transaction is processed by the third processing node 10c.

公开(公告)号：JP2000242621A

公开(公告)日：2000-09-08

申请号：JP2000031050

申请日：2000-02-08

Applicant: IBM

Inventor： CARPENTER GARY D ,  MARK EDWARD DEAN ,  DAVID BRIAN GLASCO

IPC: G06F12/08 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To reduce the number of readout requests and wait time of the nonuniform memory access computer system by interposing a 1st cache hierarchy in common and using only communication through local interconnection, and sending a copy of a specific cache line to a 2nd cache hierarchy. SOLUTION: When the 1st cache hierarchy 14 as a request source receives a request cache line through local interconnection 16, a cache controller of the 2nd cache hierarchy 14 caches the request cache line and sets its coherence state to a (Recent) state. Namely, the 1st cache hierarchy 14 as the request source among local cache hierarchy 14 holding the request cache line is interposed in common and only the communication by the local interconnection 16 is used to send a copy of the specific cache line to the 2nd cache hierarchy 14.

公开(公告)号：JP2001051959A

公开(公告)日：2001-02-23

申请号：JP2000180619

申请日：2000-06-15

Applicant: IBM

Inventor： BISHOP CHAPMAN BROCK ,  DAVID BRIAN GLASCO ,  JAMES LYLE PETERSON ,  RAMAKURISHINAN RAJAMONI ,  RONALD RIN ROCKHOLD

IPC: G06F12/00 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To section respective data processing subsystems without connecting or disconnecting any process node by allowing a constitution utility resident on a data storage device to constitute multiple process nodes selectively into a single NUMA system or multiple independent data processing systems. SOLUTION: To a data processing system, multiple process nodes 8 are connected. The respective process nodes 8 are accessed by a system memory 18 through processors 10a to 10m, a local interconnection 16, and a memory controller 17. At this time, the process nodes are constituted selectively into a single NUMA(non-uniform memory access) system or independent data processing systems. Consequently, the respective data processing subsystems can be sectioned without connecting or disconnecting any process node 8.

公开(公告)号：SG91873A1

公开(公告)日：2002-10-15

申请号：SG200003179

申请日：2000-06-06

Applicant: IBM

Inventor： BISHOP CHAPMAN BROCK ,  DAVID BRIAN GLASCO ,  JAMES LYLE PETERSON ,  RAMAKRISHNAN RAJAMONY ,  RONALD LYNN ROCKHOLD

IPC: G06F12/00 ,  G06F15/177 ,  G06F15/173

Abstract: A data processing system includes a plurality of processing nodes that each contain at least one processor and data storage. The plurality of processing nodes are coupled together by a system interconnect. The data processing system further includes a configuration utility residing in data storage within at least one of the plurality of processing nodes. The configuration utility selectively configures the plurality of processing nodes into either a single non-uniform memory access (NUMA) system or into multiple independent data processing systems through communication via the system interconnect.