公开(公告)号：US3916390A

公开(公告)日：1975-10-28

申请号：US53779674

申请日：1974-12-31

Applicant: IBM

Inventor： CHANG JOSEPH JUIFU ,  KENYON RICHARD ARTHUR

IPC: G11C11/404 ,  G11C14/00 ,  G11C16/04 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/07 ,  H01L27/10 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC classification number: G11C11/404 ,  G11C14/00 ,  G11C16/0466 ,  H01L27/0733 ,  H01L27/108

Abstract: A random access dynamic read-write FET memory system is provided with non-volatile storage of data in the event of a system power failure. The memory system includes an array of single device memory cells in which information is dynamically stored on a variable threshold non-volatile capacitor. A memory protect circuit detects system power supply failures and causes data volatively stored in the memory array to be non-volatively stored directly in the storage capacitor dielectric of each memory cell. Upon restoration of power, the non-volatively stored data is read from the array into a small auxiliary memory and the variable threshold storage capacitors are restored to their original state. Data is then returned to the memory cells in a dynamic mode.

Abstract translation: 随机访问动态读写FET存储器系统在系统电源故障的情况下提供数据的非易失性存储。 存储器系统包括单个器件存储器单元的阵列，其中信息被动态存储在可变阈值非易失性电容器上。 存储器保护电路检测系统电源故障，并且将存储在存储器阵列中的数据存储在每个存储单元的存储电容器电介质中。 在恢复电力时，将非存储数据从阵列读入小型辅助存储器，并且可变阈值存储电容器恢复到其原始状态。 然后以动态模式将数据返回到存储单元。

公开(公告)号：DE2356275A1

公开(公告)日：1974-07-04

申请号：DE2356275

申请日：1973-11-10

Applicant: IBM

Inventor： AGUSTA BENJAMIN ,  CHANG JOSEPH JUIFU

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40 ,  G11C7/00

Abstract: 1445450 Semiconductor data storage INTERNATIONAL BUSINESS MACHINES CORP 29 Nov 1973 [29 Dec 1972] 55360/73 Heading H1K A floating gate data storage FET 10 (Fig. 1) is coupled to conventional word driver 12, bit driver 14, and bit sense amplifier 15; and comprises a semiconductor substrate 16 of, e.g. N-doped Si having opposite conductivity diffused P doped source and drain regions 17, 18 separated by channel region 19. An insulant layer 21 of SiO 2 is formed over the substrate, etched into openings for source and drain diffusion and for the channel, and an oxide layer 24 of thickness to prevent tunnelling with normal I operating voltages is reformed in the channel opening. A gate electrode 25 of semiconductor material devoid of free carriers is deposited on the oxide layer 24 and is encapsulated in insulant 26, e.g. similar to layer 24 so as to float electrically. Contacts 27, 28 are applied to source and drain diffusions 17, 18 and an overlying drive gate electrode 29 is deposited on layer 25. Drain electrode 27 is coupled over 2-piston switch 30 to bit driver 14 and sense amplifier 15 or to earth, while source electrode 28 and substrate 16 are both earthed. Drive gate 29 is connected to word driver 12. Gate 25 may consume excess charge to create conductively a channel between source 17 and drain 18 to represent logic "1"; logic "0" being denoted by its absence. For logic "1" write in, the drain electrode 27 is switched to the bit driver 14 and sense amplifier 15 and the former is driven to produce ave pulse (Fig. 2 not shown) on the drain to backbias region 18, and a + ve pulse is applied to the gate electrode 29 from the word driver 12. Avalanche breakdown between drain region 18 and substrate 16 proximate to region 19 generates high energy electrons beneath the floating gate which pass thereto through layer 24 under influence of the prevailing electric fields and are stored. The accumulated electrons induce a channel between source and drain diffusions 17, 18 and the existence or non- existence of the source denotes the presence or absence of this electron charge. Low level read pulses on drain electrode 27 and drive gate electrode 29 enable detection of stored charge by the appearance of pulses on the sense amplifier 15. Charge is removed from the floating gate 25 to eliminate the induced channel and erase the storage by setting switch 30 to earth and negatively pulsing drive gate 29 from the word driver 12 so as to deplete the floating gate by avalanche breakedown into region 19. Plural short pulses may be used for erasure.

公开(公告)号：DE2557359A1

公开(公告)日：1976-07-08

申请号：DE2557359

申请日：1975-12-19

Applicant: IBM

Inventor： CHANG JOSEPH JUIFU ,  KENYON RICHARD ARTHUR

IPC: G11C11/404 ,  G11C14/00 ,  G11C16/04 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/07 ,  H01L27/10 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C11/24

Abstract: A random access dynamic read-write FET memory system is provided with non-volatile storage of data in the event of a system power failure. The memory system includes an array of single device memory cells in which information is dynamically stored on a variable threshold non-volatile capacitor. A memory protect circuit detects system power supply failures and causes data volatively stored in the memory array to be non-volatively stored directly in the storage capacitor dielectric of each memory cell. Upon restoration of power, the non-volatively stored data is read from the array into a small auxiliary memory and the variable threshold storage capacitors are restored to their original state. Data is then returned to the memory cells in a dynamic mode.

公开(公告)号：AU3530071A

公开(公告)日：1973-05-10

申请号：AU3530071

申请日：1971-11-03

Applicant: IBM

Inventor： CHANG JOSEPH JUIFU ,  SUMILAS JOHN WILLIAM

IPC: G11C19/28 ,  H01L29/423 ,  H01L29/768 ,  G11C19/00 ,  G11C11/34

Abstract: 1369606 Charge coupled devices INTERNATIONAL BUSINESS MACHINES CORP 1 Nov 1971 [4 Dec 1970] 50605/71 Heading H1K A charge coupled device comprises a semiconductor body with an electrode structure so designed that a charge zone can be stepped through the body by impressing only two time varying depletion region creating voltages on the electrodes. In the structure shown, Fig. 1, holes injected into the N-type silicon body 10 at 28 from a P-type zone or point contact with an associated gate 29, are stepped along a serpentine path defined between the parallel ridges 18a-18g of an oxide insulating layer by oppositely phased overlapping negative voltage pulses applied to interdigitated electrodes 20, 21. Along the base of each of channels 15a-15f the oxide has alternately thick and thin portions with each digit of each electrode extending over an adjacent pair of thick and thin portions. The locations of the thick and thin portions are reversed in adjacent channels so that the asymmetrical potential wells formed under each electrode digit on application of pulses thereto ensure transfer of the holes in opposite directions in the adjacent channels. In alternative forms the insulation in each channel has a sawtooth section or is of uniform thickness but with alternate sections of different dielectric constant. The preferred structure shown is made by forming a thick layer of oxide overall and then etching through masks and reforming the oxide in two stages. The electrodes, of aluminium, are then formed by deposition and are provided with contact pads 31-35 of chromium, copper, gold, tin or lead, and quartz is sputtered over the assembly to protect it. Read out is effected via strip electrode 30 to which a voltage higher than that on electrodes 20, 21 is applied, the resulting accumulation of holes beneath it affecting the forward characteristics of a heterojunction or the reverse characteristic of a PN or point contact diode located in the vicinity. A suitable detector circuit is described (Fig. 7, not shown) the output of which may be used to cause remjection of the holes at 28. The device may be associated with a buffer shift register (Fig. 8, not shown). Reference has been directed by the Comptroller to Specification 1,340,620.

公开(公告)号：DE2624157A1

公开(公告)日：1977-02-03

申请号：DE2624157

申请日：1976-05-29

Applicant: IBM

Inventor： ARNETT PATRICK CLINTON ,  CHANG JOSEPH JUIFU

IPC: H01L21/8247 ,  G11C16/04 ,  H01L27/102 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  G11C11/40 ,  G11C7/00 ,  H01L27/04

Abstract: An extremely high density memory array in which every intersection between two insulated orthogonal sets of drive lines define a nonvolatile memory device is described. Each device utilizes the area directly under the intersection of sets of lines to selectively store charges therein under control of suitable writing pulses. Reading is accomplished utilizing capacitive coupling through the device. The array comprises insulated metallic word lines orthogonal to doped bit lines defined within the surface of a semiconductor body. The insulation between the word lines and the bit lines has a dual charge state and is capable of storing charges. A unique structure is utilized whereby a highly doped layer is formed at the surface of the semiconductor body and of the same conductivity type as the body. The bit lines are composed of two distinct layers of an opposite conductivity type to that of said body wherein the layer closest to the surface is less highly doped. The selective biasing of word and bit lines causes charges to be injected into the insulation immediately between the two lines which injected charges alter the capacitance characteristics of the device and thus the signal coupling characteristic between the word and bit lines. During the write operation, an avalanche breakdown at the junction is caused to occur by heavily biasing the junction, and charge carriers are injected into the overlying insulator. The charge carriers so injected remain localized in the insulator immediately between the two lines with negligible fringing into the region outside this intersection and thus do not disturb the information on adjacent bit lines which allows extremely close placement of such adjacent lines. To erase, a voltage is supplied to cause the injected carriers to be driven out of the insulation back into the substrate. As stated previously, the reading operation utilizes the change in the coupling capacitance with a charge stored in the device and comprises introducing a signal on one line well below the breakdown voltage of the device so that the stored charge is in no way affected by any number of reading operations and detecting said signal on the other line, if coupled through.

公开(公告)号：DE2314260A1

公开(公告)日：1973-12-13

申请号：DE2314260

申请日：1973-03-22

Applicant: IBM

Inventor： CHANG JOSEPH JUIFU ,  JOSHI MADHUKAR LAXMAN ,  AGUSTA BENJAMIN

IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/00 ,  H01L29/10 ,  H01L29/423 ,  H01L29/768 ,  H01L13/00

Abstract: A semiconductor device containing in a single semiconductor body a self-aligned Field Effect Transistor and a Charge-Coupled Array having an improved capacity for storing charges. The device is formed by depositing both polysilicon and silicon nitride layers over a silicon dioxide layer on the surface of a silicon body and selectively etching these layers so that suitable dopants may be diffused or ion-implanted into selected areas of the underlying silicon body to form, in the same semiconductor body, an improved charge-coupled array having an improved self-aligned Field Effect Transistor associated therewith. This process not only results in a device in which the chance of an inversion layer under the oxide on the surface of the device is substantially reduced, but also provides a self-aligned Field Effect Transistor having a thinner gate oxide and a charge-coupled array that has an increased capacity for storing charges. The improved array so formed also has, during operation, zero spaced depletion regions so that unwanted electrical discontinuities between or within the depletion regions of the charge-coupled array are avoided. Because zero spacing is achieved by using these thin conducting layers, the metal phase lines can be made narrow thus leaving openings in the charge transfer channel making the device particularly suitable for imaging applications.

公开(公告)号：AU3944172A

公开(公告)日：1973-08-30

申请号：AU3944172

申请日：1972-02-28

Applicant: IBM

Inventor： AGUSTA BENJAMIN ,  CHANG JOSEPH JUIFU ,  DOO VEN Y ,  FERRAR PAUL A

IPC: G11C19/28 ,  H01L29/423 ,  H01L29/768 ,  G11C11/14 ,  G11C11/34