公开(公告)号：GB2596693A

公开(公告)日：2022-01-05

申请号：GB202114025

申请日：2020-03-18

Applicant: IBM

Inventor： CHARLES LEON ARVIN ,  BHUPENDER SINGH ,  RICHARD FRANCIS INDYK ,  STEVEN PAUL OSTRANDER ,  THOMAS WEISS ,  MARK WILLIAMS KAPFHAMMER

IPC: H01L23/48

Abstract: A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate.Two or more dice include components that implement functionality of the multi-die integrated circuit.The components include logic gates.The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice.Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.

公开(公告)号：GB2588354A

公开(公告)日：2021-04-21

申请号：GB202100750

申请日：2019-07-18

Applicant: IBM

Inventor： JOSHUA RUBIN ,  LAWRENCE CLEVENGER ,  CHARLES LEON ARVIN

IPC: H01L23/055 ,  H01L23/04 ,  H01L23/538 ,  H01L25/065

Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.

公开(公告)号：IL294968A

公开(公告)日：2022-09-01

申请号：IL29496822

申请日：2022-07-21

Applicant: IBM ,  CHARLES LEON ARVIN ,  BHUPENDER SINGH ,  SHIDONG LI ,  CHRIS CHRISTOPHER MUZZY ,  THOMAS ANTHONY WASSICK

Inventor： CHARLES LEON ARVIN ,  BHUPENDER SINGH ,  SHIDONG LI ,  CHRIS (CHRISTOPHER) MUZZY ,  THOMAS ANTHONY WASSICK

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065

Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

公开(公告)号：GB2588354B

公开(公告)日：2021-08-25

申请号：GB202100750

申请日：2019-07-18

Applicant: IBM

Inventor： JOSHUA RUBIN ,  LAWRENCE CLEVENGER ,  CHARLES LEON ARVIN

IPC: H01L23/055 ,  H01L23/04 ,  H01L23/538 ,  H01L25/065

Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.

公开(公告)号：GB2603404A

公开(公告)日：2022-08-03

申请号：GB202205189

申请日：2020-08-26

Applicant: IBM

Inventor： THOMAS WEISS ,  CHARLES LEON ARVIN ,  GLENN POMERANTZ ,  RACHEL OLSON ,  MARK WILLIAMS KAPFHAMMER ,  BHUPENDER SINGH

IPC: H01L23/544 ,  H01L21/56 ,  H01L21/60 ,  H01L23/538

Abstract: An alignment carrier, assembly and methods that enable the precise alignment and assembly of two or more semiconductor die using an interconnect bridge. The alignment carrier includes a substrate composed of a material that has a coefficient of thermal expansion that substantially matches that of an interconnect bridge. The alignment carrier further includes a plurality of solder balls located on the substrate and configured for alignment of two or more semiconductor die.