公开(公告)号：JP2013080971A

公开(公告)日：2013-05-02

申请号：JP2013019016

申请日：2013-02-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： LAWRENCE CLEVENGER ,  TIMOTHY JOSEPH DALTON ,  HSU LOUIS LU-CHEN ,  RADENS CARL JOHN ,  VIDYA RAMACHANDRAN ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L27/04

CPC classification number: H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming semiconductor devices having wafer back-side capacitors.SOLUTION: A method includes the following steps of: preparing an SOI substrate having a buried insulating layer inserted between a front-side active silicon layer and a back-side bulk silicon layer; forming on the front side of the SOI substrate an integrated circuit including a buried contact plug extending from the front side of the SOI substrate while penetrating through the buried insulating layer; performing back-side etching process to form a trench in the bulk silicon layer and expose an end part of the buried contact plug to the back side surface of the buried insulating layer; and forming in a trench a capacitor including a first capacitor plate, a second capacitor plate, and a capacitor dielectric layer inserted between the first and second capacitor plates. The first capacitor plate is formed to contact with the exposed end part of the buried contact plug.

Abstract translation: 要解决的问题：提供一种形成具有晶片背面电容器的半导体器件的方法。 解决方案：一种方法包括以下步骤：制备插入在前侧活性硅层和后侧体硅层之间的埋入绝缘层的SOI衬底; 在SOI衬底的正面上形成集成电路，该集成电路包括从SOI衬底的前侧延伸穿过掩埋绝缘层的埋入式接触插塞; 执行背面蚀刻工艺以在体硅层中形成沟槽，并将埋入的接触插塞的端部暴露于掩埋绝缘层的背面; 以及在沟槽中形成包括插入在所述第一和第二电容器板之间的第一电容器板，第二电容器板和电容器电介质层的电容器。 第一电容器板形成为与埋入式接触插塞的暴露端部接触。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2000195860A

公开(公告)日：2000-07-14

申请号：JP37512499

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： SCHNABEL RAINER FLORIAN ,  RONALD PHILLIPI ,  HOINKIS MARK ,  WEBER STEFAN ,  ROY IGARUDEN ,  WEIGAND PETER ,  LAWRENCE CLEVENGER

IPC: H01L23/52 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To increase the electromigration lifetime of a semiconductor device by stacking a liner by an ionizing metal plasma physical deposition method, thereby reducing the mass carriage by electromigration. SOLUTION: A dielectric layer is made on a substrate. The dielectric layer is patterned, and a contact hole 26 is made, and conductive material is stacked on a dielectric layer so as to fill the contact hole 26 and cover the dielectric layer. Next, excess material is removed by polishing from the surface 29 so as to make a flat surface for an additional layer. Next, a liner 40 is stacked on the dielectric layer 29. This liner consists of a material having high electromigration resistance. For example, titanium(Ti) and its alloy tantalum(Ta) and its alloy, or TiN or Tan is included as such a liner material. This liner 40 is stacked, using an ionizing metal plasma physical deposition method.

公开(公告)号：GB2576466A

公开(公告)日：2020-02-19

申请号：GB201917751

申请日：2018-05-29

Applicant: IBM

Inventor： BENJAMIN DAVID BRIGGS ,  LEIGH ANNE CLEVENGER ,  MICHAEL RIZZOLO ,  MARYAM ASHOORI ,  SPYRIDON SKORDAS ,  LAWRENCE CLEVENGER ,  JUSTIN CANAPERI

IPC: G06F3/041

Abstract: A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.

公开(公告)号：GB2603346A

公开(公告)日：2022-08-03

申请号：GB202204025

申请日：2020-08-14

Applicant: IBM

Inventor： NICHOLAS ANTHONY LANZILLO ,  HOSADURGA SHOBHA ,  HUAI HUANG ,  JUNLI WANG ,  KOICHI MOTOYAMA ,  CHRISTOPHER PENNY ,  LAWRENCE CLEVENGER

IPC: H01L21/768

Abstract: Techniques for forming trapezoidal-shaped interconnects are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench(es) in a dielectric having a V-shaped profile with a rounded bottom; depositing a liner into the trench(es) using PVD which opens-up the trench(es) creating a trapezoidal-shaped profile in the trench(es); removing the liner from the trench(es) selective to the dielectric whereby, following the removing, the trench(es) having the trapezoidal-shaped profile remains in the dielectric; depositing a conformal barrier layer into and lining the trench(es) having the trapezoidal-shaped profile; depositing a conductor into and filling the trench(es) having the trapezoidal-shaped profile over the conformal barrier layer; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided.

公开(公告)号：GB2588354A

公开(公告)日：2021-04-21

申请号：GB202100750

申请日：2019-07-18

Applicant: IBM

Inventor： JOSHUA RUBIN ,  LAWRENCE CLEVENGER ,  CHARLES LEON ARVIN

IPC: H01L23/055 ,  H01L23/04 ,  H01L23/538 ,  H01L25/065

Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.

公开(公告)号：GB2603346B

公开(公告)日：2023-12-20

申请号：GB202204025

申请日：2020-08-14

Applicant: IBM

Inventor： NICHOLAS ANTHONY LANZILLO ,  HOSADURGA SHOBHA ,  HUAI HUANG ,  JUNLI WANG ,  KOICHI MOTOYAMA ,  CHRISTOPHER PENNY ,  LAWRENCE CLEVENGER

IPC: H01L21/768

Abstract: Techniques for forming trapezoidal-shaped interconnects are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench(es) in a dielectric having a V-shaped profile with a rounded bottom; depositing a liner into the trench(es) using PVD which opens-up the trench(es) creating a trapezoidal-shaped profile in the trench(es); removing the liner from the trench(es) selective to the dielectric whereby, following the removing, the trench(es) having the trapezoidal-shaped profile remains in the dielectric; depositing a conformal barrier layer into and lining the trench(es) having the trapezoidal-shaped profile; depositing a conductor into and filling the trench(es) having the trapezoidal-shaped profile over the conformal barrier layer; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided.

公开(公告)号：GB2581082B

公开(公告)日：2022-07-06

申请号：GB202005861

申请日：2018-11-01

Applicant: IBM

Inventor： TAKASHI ANDO ,  CHIH-CHAO YANG ,  BENJAMIN BRIGGS ,  MICHAEL RIZZOLO ,  LAWRENCE CLEVENGER

IPC: H01L45/00 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24

Abstract: A method is presented for forming a semiconductor device. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form a plurality of trenches for receiving a first conducting material, forming a resistive switching memory element over at least one trench of the plurality of trenches, the resistive switching memory element having a conducting cap formed thereon, and depositing a dielectric cap over the trenches. The method further includes etching portions of the insulating layer to expose a section of the dielectric cap formed over the resistive switching memory element, etching the exposed section of the dielectric cap to expose the conducting cap of the resistive switching memory element, and forming a barrier layer in direct contact with the exposed section of the conducting cap.

公开(公告)号：GB2596742A

公开(公告)日：2022-01-05

申请号：GB202114702

申请日：2020-03-26

Applicant: IBM

Inventor： HSUEH-CHUNG CHEN ,  YONGAN XU ,  YANN MIGNOT ,  JAMES KELLY ,  LAWRENCE CLEVENGER

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/768

Abstract: A technique relates to a method and a semiconductor device. Mandrels are formed on a substrate, the mandrels including a first metal layer. A second metal layer is formed on the substrate adjacent to the first metal layer, the first and second metal layers being separated by spacer material.

公开(公告)号：GB2601100A

公开(公告)日：2022-05-18

申请号：GB202204077

申请日：2020-09-08

Applicant: IBM

Inventor： MICHAEL RIZZOLO ,  NICHOLAS ANTHONY LANZILLO ,  BENJAMIN DAVID BRIGGS ,  LAWRENCE CLEVENGER

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/12

Abstract: A method for forming an MRAM device includes: forming MTJs (202) on interconnects (106) embedded in a first dielectric (102); depositing an encapsulation layer (204) over the MTJs (202); burying the MTJs (202) in a second dielectric (206); patterning a trench (302') in the second dielectric (206) over the MTJs (202) exposing the encapsulation layer (204) over tops of the MTJs (202) which creates a topography at the trench (302') bottom; forming a metal line (904) in the trench (302') over the topography; recessing the metal line (904) which breaks up the metal line (904) into segments (904a, 904b) separated by exposed peaks of the encapsulation layer (204); recessing the exposed peaks of the encapsulation layer (204) to form recesses at the tops of the MTJs (202); and forming self-aligned contacts (1202) in the recesses. An MRAM device is also provided.

公开(公告)号：GB2588354B

公开(公告)日：2021-08-25

申请号：GB202100750

申请日：2019-07-18

Applicant: IBM

Inventor： JOSHUA RUBIN ,  LAWRENCE CLEVENGER ,  CHARLES LEON ARVIN

IPC: H01L23/055 ,  H01L23/04 ,  H01L23/538 ,  H01L25/065

Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.