公开(公告)号：GB2579729A

公开(公告)日：2020-07-01

申请号：GB202001670

申请日：2018-07-18

Applicant: IBM

Inventor： JOSHUA RUBIN ,  ARVIND KUMAR

IPC: H01L27/22 ,  H01L43/12

Abstract: A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.

公开(公告)号：GB2588354A

公开(公告)日：2021-04-21

申请号：GB202100750

申请日：2019-07-18

Applicant: IBM

Inventor： JOSHUA RUBIN ,  LAWRENCE CLEVENGER ,  CHARLES LEON ARVIN

IPC: H01L23/055 ,  H01L23/04 ,  H01L23/538 ,  H01L25/065

Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.

公开(公告)号：GB2579729B

公开(公告)日：2022-06-08

申请号：GB202001670

申请日：2018-07-18

Applicant: IBM

Inventor： JOSHUA RUBIN ,  ARVIND KUMAR

IPC: H01L27/22 ,  H01L43/12

Abstract: A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.

公开(公告)号：GB2588354B

公开(公告)日：2021-08-25

申请号：GB202100750

申请日：2019-07-18

Applicant: IBM

Inventor： JOSHUA RUBIN ,  LAWRENCE CLEVENGER ,  CHARLES LEON ARVIN

IPC: H01L23/055 ,  H01L23/04 ,  H01L23/538 ,  H01L25/065

Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.