公开(公告)号：JP2007134721A

公开(公告)日：2007-05-31

申请号：JP2006304611

申请日：2006-11-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NOWAK EDWARD J ,  CHEN JIA

IPC: H01L29/786

CPC classification number: H01L51/055 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/94

Abstract: PROBLEM TO BE SOLVED: To provide a stable p-type CNTFET and a stable n-type CNTFET by disclosing a CNT technology that overcomes the intrinsic ambipolar properties of CNTFETs.
SOLUTION: In order to overcome the ambipolar properties of a CNTFET, source/drain gates 125 are introduced below a CNT 110 opposite source/drain electrodes 105. In this case, the source/drain gates 125 are used to apply either a positive or negative voltage to the ends of a CNT 111 so as to configure the corresponding FET as either an n-type or p-type CNTFET, respectively. In addition, a complementary CNT can be incorporated into a device by two adjacent CNTFETs configured such that one is an n-type CNTFET and the other is a p-type CNTFET.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过公开克服CNTFET的固有双极性质的CNT技术来提供稳定的p型CNTFET和稳定的n型CNTFET。 解决方案：为了克服CNTFET的双极性，源极/漏极栅极125被引入CNT 110相对的源极/漏极105的下方。在这种情况下，源极/漏极门125用于施加 正电压或负电压到CNT 111的端部，以便将相应的FET分别构造为n型或p型CNTFET。 此外，互补的CNT可以通过配置成使得一个是n型CNTFET并且另一个是p型CNTFET的两个相邻的CNTFET被并入到器件中。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004336056A

公开(公告)日：2004-11-25

申请号：JP2004137499

申请日：2004-05-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN JIA ,  GRASSMANN ANDREAS E

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L21/823842

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for a method for manufacturing a device having different type transistors.
SOLUTION: Gates of different type transistors in a device include different materials. The method comprises the steps of: depositing a silicon layer on a gate insulating layer; depositing a first type gate material on the silicon layer; removing the first type gate material from the region in which a second type gate is formed; depositing a second type gate material on the silicon layer in the region from which the first type gate material has been removed; simultaneously patterning in order to form the first type gate material and the second type gate material into the first type gate and the second type gate; and changing the two type gate materials by annealing.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供用于制造具有不同类型晶体管的器件的方法的方法和结构。 解决方案：器件中不同类型晶体管的栅极包括不同的材料。 该方法包括以下步骤：在栅极绝缘层上沉积硅层; 在硅层上沉积第一种类型的栅极材料; 从形成有第二型栅极的区域去除第一类型的栅极材料; 在已经去除了第一类型栅极材料的区域中的硅层上沉积第二种栅极材料; 同时构图以形成第一类型栅极材料和第二类型栅极材料进入第一类型栅极和第二类型栅极; 并通过退火改变两种栅极材料。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2006240898A

公开(公告)日：2006-09-14

申请号：JP2005055790

申请日：2005-03-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN JIA ,  ALI AFUZARI-ARUDAKANI ,  KLINKE CHRISTIAN ,  SOLOMON PAUL M ,  AVOURIS PHAEDON

IPC: C01B31/02 ,  H01L21/336 ,  H01L29/06 ,  H01L29/786 ,  H01L51/05

Abstract: PROBLEM TO BE SOLVED: To provide a method for doping carbon nanotube by a solution treatment, a semiconductor device and a method of forming the semiconductor device. SOLUTION: This doping method for carbon nanotube includes a process for exposing the carbon nanotube to a one-electron oxidizer in a solution phase. Further, there are provided a method of forming a carbon nanotube FET device and also a semiconductor device. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 解决的问题：提供一种通过固溶处理掺杂碳纳米管的方法，半导体器件和形成半导体器件的方法。 解决方案：用于碳纳米管的这种掺杂方法包括在溶液相中将碳纳米管暴露于单电子氧化剂的方法。 此外，提供了形成碳纳米管FET器件以及半导体器件的方法。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：EP1671376A4

公开(公告)日：2008-09-03

申请号：EP04785971

申请日：2004-06-30

Applicant: IBM

Inventor： CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

IPC: H01L21/28 ,  H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119

CPC classification number: H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer (41) on the gate dielectric (43). The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe (45) with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer (47), (3) to 4A thick. The thin SiO2 or SixGeyOZ interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of a subsequently deposited layer of cobalt. This gate electrode stack structure is used for both nFETs.and pFETs.

Abstract translation: 场效应晶体管器件的多层栅电极堆叠结构形成在栅电介质（43）上的硅纳米晶种层（41）上。 使用原位快速热化学气相沉积（RTCVD），硅纳米晶体层的小晶粒尺寸允许沉积具有高达至少70％的[Ge]的均匀且连续的多晶SiGe（45）层。 在快速降低的温度下在氧气环境中原位净化沉积室导致SiO2或SixGeyOz薄界面层（47），（3）至4A厚。 薄SiO2或SixGeyOZ界面层足够薄且不连续以提供对栅极电流流动的小阻力，但具有足够的[O]以在热处理期间有效阻挡向上的Ge扩散，从而允许随后沉积的钴层发生硅化。 该栅极电极堆叠结构用于nFET和pFET。

公开(公告)号：WO2005041252A2

公开(公告)日：2005-05-06

申请号：PCT/US2004020907

申请日：2004-06-30

Applicant: IBM ,  CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

Inventor： CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

IPC: H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119 ,  H01L

CPC classification number: H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer (41) on the gate dielectric (43). The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe (45) with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer (47), (3) to 4A thick. The thin SiO2 or SixGeyOZ interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of a subsequently deposited layer of cobalt. This gate electrode stack structure is used for both nFETs.and pFETs.

Abstract translation: 在栅极电介质（43）上的硅纳米晶种子层（41）上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积具有高达至少70％的[Ge]的均匀且连续的多晶硅（45）层。 在快速降低的温度下，氧气环境中沉积室的原位吹扫导致薄的SiO 2或SixGeyOz界面层（47），（3）至4A厚。 薄的SiO 2或SixGeyOZ界面层是足够薄且不连续的，以提供对栅极电流的很小的阻力，但是具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许随后沉积的钴的硅化物。 该栅电极堆叠结构用于nFET和pFET。

公开(公告)号：WO2005041252B1

公开(公告)日：2005-09-09

申请号：PCT/US2004020907

申请日：2004-06-30

Applicant: IBM ,  CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

Inventor： CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

IPC: H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119

CPC classification number: H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer (41) on the gate dielectric (43). The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe (45) with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer (47), (3) to 4A thick. The thin SiO2 or SixGeyOZ interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of a subsequently deposited layer of cobalt. This gate electrode stack structure is used for both nFETs.and pFETs.