公开(公告)号：EP1671376A4

公开(公告)日：2008-09-03

申请号：EP04785971

申请日：2004-06-30

Applicant: IBM

Inventor： CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

IPC: H01L21/28 ,  H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119

CPC classification number: H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer (41) on the gate dielectric (43). The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe (45) with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer (47), (3) to 4A thick. The thin SiO2 or SixGeyOZ interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of a subsequently deposited layer of cobalt. This gate electrode stack structure is used for both nFETs.and pFETs.

Abstract translation: 场效应晶体管器件的多层栅电极堆叠结构形成在栅电介质（43）上的硅纳米晶种层（41）上。 使用原位快速热化学气相沉积（RTCVD），硅纳米晶体层的小晶粒尺寸允许沉积具有高达至少70％的[Ge]的均匀且连续的多晶SiGe（45）层。 在快速降低的温度下在氧气环境中原位净化沉积室导致SiO2或SixGeyOz薄界面层（47），（3）至4A厚。 薄SiO2或SixGeyOZ界面层足够薄且不连续以提供对栅极电流流动的小阻力，但具有足够的[O]以在热处理期间有效阻挡向上的Ge扩散，从而允许随后沉积的钴层发生硅化。 该栅极电极堆叠结构用于nFET和pFET。

公开(公告)号：WO2005041252A2

公开(公告)日：2005-05-06

申请号：PCT/US2004020907

申请日：2004-06-30

Applicant: IBM ,  CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

Inventor： CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

IPC: H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119 ,  H01L

CPC classification number: H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer (41) on the gate dielectric (43). The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe (45) with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer (47), (3) to 4A thick. The thin SiO2 or SixGeyOZ interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of a subsequently deposited layer of cobalt. This gate electrode stack structure is used for both nFETs.and pFETs.

Abstract translation: 在栅极电介质（43）上的硅纳米晶种子层（41）上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积具有高达至少70％的[Ge]的均匀且连续的多晶硅（45）层。 在快速降低的温度下，氧气环境中沉积室的原位吹扫导致薄的SiO 2或SixGeyOz界面层（47），（3）至4A厚。 薄的SiO 2或SixGeyOZ界面层是足够薄且不连续的，以提供对栅极电流的很小的阻力，但是具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许随后沉积的钴的硅化物。 该栅电极堆叠结构用于nFET和pFET。

公开(公告)号：WO2005041252B1

公开(公告)日：2005-09-09

申请号：PCT/US2004020907

申请日：2004-06-30

Applicant: IBM ,  CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

Inventor： CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

IPC: H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119

CPC classification number: H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer (41) on the gate dielectric (43). The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe (45) with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer (47), (3) to 4A thick. The thin SiO2 or SixGeyOZ interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of a subsequently deposited layer of cobalt. This gate electrode stack structure is used for both nFETs.and pFETs.