公开(公告)号：EP1794786A4

公开(公告)日：2008-12-24

申请号：EP05785191

申请日：2005-06-21

Applicant: IBM

Inventor： CHAN KEVIN K ,  GUARINI KATHRYN W ,  IEONG MEIKEL ,  RIM KERN ,  YANG MIN

IPC: H01L29/04 ,  H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/036 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/045 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/823807 ,  H01L29/1054

Abstract: A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psuedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600ºC and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described comprising the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HC1 acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a RMS roughness of less than 0.1 nm.

Abstract translation: 描述了一种用于导电载体的结构和形成方法，该结构包括在<110>中具有上表面的Si或SiGe的单晶衬底以及具有不同于衬底的Ge浓度的伪晶体或外延层，由此该伪晶体层 正处于紧张状态。 描述了用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中形成假性或外延层的步骤，通过将工具中的温度提高至约600℃并且将含Si气体和Ge 含有气体。 描述了用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底分别浸入一系列含有臭氧，稀HF，去离子水，HCl酸和去离子水的浴中，接着在惰性气氛中干燥衬底 以获得无杂质且具有小于0.1nm的RMS粗糙度的基材表面。

公开(公告)号：EP1671376A4

公开(公告)日：2008-09-03

申请号：EP04785971

申请日：2004-06-30

Applicant: IBM

Inventor： CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

IPC: H01L21/28 ,  H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119

CPC classification number: H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer (41) on the gate dielectric (43). The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe (45) with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer (47), (3) to 4A thick. The thin SiO2 or SixGeyOZ interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of a subsequently deposited layer of cobalt. This gate electrode stack structure is used for both nFETs.and pFETs.

Abstract translation: 场效应晶体管器件的多层栅电极堆叠结构形成在栅电介质（43）上的硅纳米晶种层（41）上。 使用原位快速热化学气相沉积（RTCVD），硅纳米晶体层的小晶粒尺寸允许沉积具有高达至少70％的[Ge]的均匀且连续的多晶SiGe（45）层。 在快速降低的温度下在氧气环境中原位净化沉积室导致SiO2或SixGeyOz薄界面层（47），（3）至4A厚。 薄SiO2或SixGeyOZ界面层足够薄且不连续以提供对栅极电流流动的小阻力，但具有足够的[O]以在热处理期间有效阻挡向上的Ge扩散，从而允许随后沉积的钴层发生硅化。 该栅极电极堆叠结构用于nFET和pFET。

公开(公告)号：JP2006013503A

公开(公告)日：2006-01-12

申请号：JP2005182180

申请日：2005-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAKRAVARTI ASHIMA B ,  JUDSON HOLT ,  CHAN KEVIN K ,  DESHPANDE SADANAND V ,  JAGANNATHAN RANGARAJAN

IPC: H01L21/318 ,  C23C16/30 ,  C23C16/34 ,  C23C16/40 ,  H01L21/283 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7843 ,  C23C16/308 ,  C23C16/34 ,  C23C16/401 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/3143 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/31608 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834 ,  H01L29/7833 ,  H01L29/78675

Abstract: PROBLEM TO BE SOLVED: To provide films, especially silicon nitride films, silicon oxide films, silicon oxynitride films, and silicon carbide films, which are formed more easily at a higher deposition rate in comparison with conventional processes.
SOLUTION: Adding at least one non-silicon precursor (such as a germanium precursor and a carbon precursor) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate, and/or allows properties, such as the stress, of the film to be adjusted. Also, in a doped silicon oxide or doped silicon nitride or any other doped structure, the presence of a dopant can be used for measuring a signal (marking) associated with the dopant as an etch stop, or in other cases, for achieving control during etching.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：与常规方法相比，提供更容易形成的膜，特别是氮化硅膜，氧化硅膜，氮氧化硅膜和碳化硅膜。 解决方案：在形成氮化硅，氧化硅，氮氧化硅或碳化硅膜期间添加至少一种非硅前体（例如锗前体和碳前体）改善沉积速率和/或允许性质 ，如压力，要调整的电影。 此外，在掺杂氧化硅或掺杂氮化硅或任何其它掺杂结构中，掺杂剂的存在可用于测量与掺杂剂相关联的信号（标记）作为蚀刻停止，或在其它情况下用于在 蚀刻。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2005067677A2

公开(公告)日：2005-07-28

申请号：PCT/US2005000072

申请日：2005-01-04

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHAN KEVIN K ,  CHIDAMBARRAO DURESETI ,  CHRISTIANSEN SILKE H ,  CHU JACK O ,  DOMENICUCCI ANTHONY G ,  LEE KAM-LEUNG ,  MOCUTA ANDA C ,  OTT JOHN A ,  OUYANG QIQING C

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.

Abstract translation: 应变Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。 松弛的第一材料和应变的第二材料形成FinFET的鳍。

公开(公告)号：WO2005041252B1

公开(公告)日：2005-09-09

申请号：PCT/US2004020907

申请日：2004-06-30

Applicant: IBM ,  CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

Inventor： CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

IPC: H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119

CPC classification number: H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer (41) on the gate dielectric (43). The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe (45) with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer (47), (3) to 4A thick. The thin SiO2 or SixGeyOZ interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of a subsequently deposited layer of cobalt. This gate electrode stack structure is used for both nFETs.and pFETs.

公开(公告)号：JP2005340816A

公开(公告)日：2005-12-08

申请号：JP2005147746

申请日：2005-05-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAN KEVIN K ,  MILLER ROBER J ,  JONES ERIN C ,  AJMERA ATUL

IPC: H01L21/225 ,  C30B1/00 ,  H01L21/20 ,  H01L21/205 ,  H01L21/316 ,  H01L21/331 ,  H01L21/336 ,  H01L21/36 ,  H01L21/8222 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/0843 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/2252 ,  H01L21/31695 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a manufacturing method of a MOSFET device having a polycrystalline SiGe junction.
SOLUTION: Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers produce a SiGe junction. The deposited layers are doped, and then the dopants are outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junction.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有多晶SiGe结的MOSFET器件的结构和制造方法。 解决方案：Ge选择性地生长在Si上，而Si选择性地生长在Ge上。 Ge和Si层的交替沉积产生SiGe结。 沉积的层被掺杂，然后掺杂物向外扩散到器件本体中。 多晶Ge和Si层之间的薄多孔氧化物层增强了SiGe结的各向同性。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2002094328A

公开(公告)日：2002-03-29

申请号：JP2001180600

申请日：2001-06-14

Applicant: IBM

Inventor： CHAN KEVIN K ,  JHANES CHRISTOPHER ,  SHI LEATHEN ,  SPEIDELL JAMES L ,  ZIEGLER JAMES F

IPC: B81B3/00 ,  B81B7/00 ,  B81C1/00 ,  H03D7/00 ,  H03H3/007 ,  H03H9/10 ,  H03H9/24 ,  H03H9/46 ,  H04B1/26

Abstract: PROBLEM TO BE SOLVED: To provide a communication signal mixing/filtering system that employs a capsulated microelectric mechanical system(MEMS) device, and to provide its manufacturing method. SOLUTION: The microelectric mechanical system(MEMS) of a simple single structure combines a signal mixing step and a filtering step. The MEMS device is further reduced in size and made less expensive, and has higher reliability in its structure and operation as compared with those of the existing device adopting the conventional technology.

公开(公告)号：WO2011133339A3

公开(公告)日：2012-03-08

申请号：PCT/US2011031693

申请日：2011-04-08

Applicant: IBM ,  CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8228 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底12的上表面上的FET栅极堆叠18. FET栅极堆叠包括在FET栅极堆叠的覆盖区处位于半导体衬底内的源极和漏极延伸区域28。 器件沟道40也存在于源极延伸区域和漏极延伸区域之间以及栅极堆叠层下方。 该结构还包括位于FET栅极堆叠的相对侧并且位于半导体衬底内的嵌入式应力元件34。 每个嵌入的应力元件包括第一外延36掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延的上层 38掺杂的半导体材料位于下层的顶部。 与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。 该结构还包括位于每个嵌入的应力元件的上层内的掺杂剂单层。 掺杂剂的单层与源极延伸区域或漏极延伸区域的边缘直接接触。

公开(公告)号：WO2011056336A3

公开(公告)日：2011-07-28

申请号：PCT/US2010051383

申请日：2010-10-05

Applicant: IBM ,  YIN HAIZHOU ,  WANG XINHUI ,  CHAN KEVIN K ,  REN ZHIBIN

Inventor： YIN HAIZHOU ,  WANG XINHUI ,  CHAN KEVIN K ,  REN ZHIBIN

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/26586 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7835

Abstract: The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.

Abstract translation: 本发明提供了形成非对称场效应晶体管的方法。 所述方法包括在半导体衬底的顶部上形成栅极结构，所述栅极结构包括栅极叠层和邻近所述栅极堆叠的侧壁的间隔物，并且具有与所述第一侧相对的第一侧和第二侧; 从衬底中的栅极结构的第一侧进行成角度的离子注入，从而形成与第一侧相邻的离子注入区域，其中栅极结构防止成角度的离子注入到达邻近第二侧的衬底 门结构; 以及在栅极结构的第一和第二侧在衬底上进行外延生长。 结果，在离子注入区域上的外延生长比经历无离子注入的区域慢得多。 通过外延生长形成到栅极结构的第二侧的源极区域的高度高于通过外延生长形成于栅极结构的第一侧的漏极区域的高度。 还提供了由此形成的半导体结构。

公开(公告)号：WO2011162977A3

公开(公告)日：2012-03-15

申请号：PCT/US2011039892

申请日：2011-06-10

Applicant: IBM ,  CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).

Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底（12）的上表面上的至少一个FET栅叠层（18）。 所述至少一个FET栅极堆叠包括位于所述至少一个FET栅极堆叠中的覆盖区内的所述半导体衬底内的源极和漏极延伸区域（28）。 器件通道（40）也存在于源极和漏极延伸区域（28）之间并且在至少一个栅极堆叠（18）下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且在半导体衬底内的嵌入式应力元件（33）。 每个嵌入式应力元件包括从底部到顶部具有不同于半导体衬底的晶格常数的晶格常数的第一外延掺杂半导体材料（35）的第一层，并且在器件沟道中施加应变， 位于第一层顶部的第二外延掺杂半导体材料（36）的第二层和位于第二层的上表面上的掺杂剂的Δ单层。 该结构还包括直接位于三角单层（37）的上表面上的金属半导体合金接触（45）。