公开(公告)号：EP1979949A4

公开(公告)日：2010-08-25

申请号：EP07710011

申请日：2007-01-09

Applicant: IBM

Inventor： CHENG KANGGUO ,  RASSEL ROBERT M

IPC: H01L29/94 ,  H01L21/02 ,  H01L21/334 ,  H01L27/01 ,  H01L27/06

CPC classification number: H01L29/945 ,  H01L27/016 ,  H01L27/0682 ,  H01L28/20 ,  H01L29/66181

公开(公告)号：EP2160757A4

公开(公告)日：2010-08-04

申请号：EP08780748

申请日：2008-06-04

Applicant: IBM

Inventor： CHENG KANGGUO

IPC: H01L21/336 ,  H01L29/49

CPC classification number: H01L29/4991 ,  H01L21/28194 ,  H01L29/42368 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66583 ,  Y10S438/926

公开(公告)号：WO2007137946A3

公开(公告)日：2008-03-13

申请号：PCT/EP2007054769

申请日：2007-05-16

Applicant: IBM ,  IBM UK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA

Inventor： CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA

IPC: H01L29/94 ,  H01L21/334

CPC classification number: H01L29/945 ,  H01L29/66181

Abstract: A semiconductor fabrication method comprises steps of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. The method further comprises the steps of removing portions of the blocking layer on the {110} side wall surfaces without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.

Abstract translation: 半导体制造方法包括提供半导体结构的步骤。 半导体结构包括半导体衬底，半导体衬底中的沟槽。 沟槽包括侧壁，其包括{100}侧壁表面和{110}侧壁表面。 半导体结构还包括在{100}侧壁表面和{110}侧壁表面上的阻挡层。 该方法还包括以下步骤：除去{110}侧壁表面上的阻挡层的部分，而不去除{100}侧壁表面上的阻挡层的部分，使得{110}侧壁表面暴露于周围 周围。

公开(公告)号：WO2007023011B1

公开(公告)日：2007-07-12

申请号：PCT/EP2006063581

申请日：2006-06-27

Applicant: IBM ,  IBM UK ,  MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

Inventor： MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

Abstract: A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

Abstract translation: 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

公开(公告)号：EP2008300A4

公开(公告)日：2012-05-23

申请号：EP07758889

申请日：2007-03-20

Applicant: IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  CHENG KANGGUO

IPC: H01L21/44 ,  C01B32/50 ,  H01L21/00 ,  H01L21/84 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L29/7827 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10841 ,  H01L27/10876 ,  H01L29/66666 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of forming a body contact for a semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.

公开(公告)号：EP1812966A4

公开(公告)日：2010-07-14

申请号：EP05848854

申请日：2005-11-09

Applicant: IBM

Inventor： CHENG KANGGUO ,  RADENS CARL J

IPC: H01L21/8242

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/1203 ,  H01L27/1207

公开(公告)号：EP1977425A4

公开(公告)日：2009-04-29

申请号：EP07710032

申请日：2007-01-10

Applicant: IBM

Inventor： CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

IPC: G11C11/24 ,  H01L21/8242

CPC classification number: G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

Abstract: An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors (102) connected together as a unitary source of capacitance. A first access transistor (104) is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor (106) is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.

公开(公告)号：WO2007023011A2

公开(公告)日：2007-03-01

申请号：PCT/EP2006063581

申请日：2006-06-27

Applicant: IBM ,  IBM UK ,  MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

Inventor： MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/12

CPC classification number: H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

Abstract: A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

Abstract translation: 用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储器单元和工艺序列。 具体而言，本发明提供了与现有SOI CMOS技术兼容的密集，高性能SRAM单元替换。 本领域已知各种增益单元布局。 本发明通过提供用SOI CMOS制造的密集布局来改进现有技术。 一般而言，存储器单元包括分别设置有栅极，源极和漏极的第一晶体管; 第二晶体管，分别具有第一栅极，第二栅极，源极和漏极; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

公开(公告)号：WO2007082227A3

公开(公告)日：2008-09-25

申请号：PCT/US2007060317

申请日：2007-01-10

Applicant: IBM ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

Inventor： CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

IPC: G11C11/24 ,  H01L21/8242

CPC classification number: G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

Abstract: An integrated circuit is provided which includes a memory (100) having multiple ports per memory cell for accessing a data bit with each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plural of capacitors (102) connected together as a unitary source of capacitance (S). A first access transistor (104) is coupled between a firs one of the plurality of capacitors and a first bitline (RBL) and a second access transistor (106) is coupled between a second one of th plurality of capacitors and a second bitline (WBL) In each memory cell, a gate of the first access transistor (104) is connected to a fi wordline (RWL) and a gate of the second access transistor (106) is connected to a second wordline (WWL)

Abstract translation: 提供一种集成电路，其包括每个存储器单元具有多个端口的存储器（100），用于利用多个存储器单元中的每一个访问数据位。 这样的存储器包括存储单元阵列，其中每个存储单元包括连接在一起的多个电容器（102）作为电容（S）的整体源。 第一存取晶体管（104）耦合在所述多个电容器中的第一个电容器中，并且第一位线（RBL）和第二存取晶体管（106）耦合在所述多个电容器中的第二电容器和第二位线（WBL ）在每个存储单元中，第一存取晶体管（104）的栅极连接到fi字线（RWL），第二存取晶体管（106）的栅极连接到第二字线（WWL）

公开(公告)号：JP2007123880A

公开(公告)日：2007-05-17

申请号：JP2006286977

申请日：2006-10-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHU HUILONG ,  CHENG KANGGUO

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/786

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a field effect transistor (FET) including a source side semiconductor, a drain side semiconductor, and a gate.
SOLUTION: The source side semiconductor is made of a high-mobility semiconductor material, and the drain side semiconductor is made of a low-leakage semiconductor material. According to one embodiment, the FET is a metal-oxide-semiconductor field effect transistor (MOSFET). A method for manufacturing the FET is also provided.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种包括源极半导体，漏极侧半导体和栅极的场效应晶体管（FET）。 解决方案：源极半导体由高迁移率半导体材料制成，漏极侧半导体由低泄漏半导体材料制成。 根据一个实施例，FET是金属氧化物半导体场效应晶体管（MOSFET）。 还提供了一种用于制造FET的方法。 版权所有（C）2007，JPO＆INPIT