公开(公告)号：WO2007023011A2

公开(公告)日：2007-03-01

申请号：PCT/EP2006063581

申请日：2006-06-27

Applicant: IBM ,  IBM UK ,  MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

Inventor： MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/12

CPC classification number: H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

Abstract: A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

Abstract translation: 用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储器单元和工艺序列。 具体而言，本发明提供了与现有SOI CMOS技术兼容的密集，高性能SRAM单元替换。 本领域已知各种增益单元布局。 本发明通过提供用SOI CMOS制造的密集布局来改进现有技术。 一般而言，存储器单元包括分别设置有栅极，源极和漏极的第一晶体管; 第二晶体管，分别具有第一栅极，第二栅极，源极和漏极; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

公开(公告)号：WO2007023011B1

公开(公告)日：2007-07-12

申请号：PCT/EP2006063581

申请日：2006-06-27

Applicant: IBM ,  IBM UK ,  MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

Inventor： MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

Abstract: A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

Abstract translation: 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

公开(公告)号：EP1977425A4

公开(公告)日：2009-04-29

申请号：EP07710032

申请日：2007-01-10

Applicant: IBM

Inventor： CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

IPC: G11C11/24 ,  H01L21/8242

CPC classification number: G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

Abstract: An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors (102) connected together as a unitary source of capacitance. A first access transistor (104) is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor (106) is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.

公开(公告)号：JP2005175478A

公开(公告)日：2005-06-30

申请号：JP2004353482

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN XIANGDONG ,  CHIDAMBARRAO DURESETI ,  WANG GENG

IPC: H01L27/08 ,  H01L21/8238 ,  H01L27/085 ,  H01L27/092 ,  H01L27/12 ,  H01L29/745 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/783

Abstract: PROBLEM TO BE SOLVED: To provide a MOSFET which dynamically varies the threshold voltage on an SOI.
SOLUTION: When a body control contact is provided adjacent to a transistor and between the transistor and a contact to a substrate or a well in which the transistor is formed, the substrate of the transistor can be connected to and disconnected from a zero (ground) or substantially arbitrary low voltage in accordance with control signals applied to the gate of the transistor to cause the transistor to exhibit a variable threshold, resulting in good performance maintained even at low supply voltages and reduced power consumption/dissipation, which are particularly advantageous in portable electronic devices. Floating body effects (when the transistor substrate is disconnected from a voltage source in the "on" state) are avoided because the substrate is discharged when the transistor is switched to the "off" state. The transistor configuration can be used with n-type and p-type transistors in the case of complementary pairs or the like.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在SOI上动态地改变阈值电压的MOSFET。 解决方案：当身体控制触点设置在晶体管附近以及晶体管与形成晶体管的衬底或阱的触点之间时，晶体管的衬底可以连接到零点 （接地）或基本上任意的低电压，根据施加到晶体管的栅极的控制信号，以使晶体管呈现可变阈值，导致即使在低电源电压下也保持良好的性能，并且降低功耗/耗散，这特别是 有利于便携式电子设备。 避免浮体效应（当晶体管基板从“导通”状态的电压源断开时），因为当晶体管切换到“关闭”状态时，衬底被放电。 在互补对等的情况下，晶体管配置可以与n型和p型晶体管一起使用。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2007082227A3

公开(公告)日：2008-09-25

申请号：PCT/US2007060317

申请日：2007-01-10

Applicant: IBM ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

Inventor： CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

IPC: G11C11/24 ,  H01L21/8242

CPC classification number: G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

Abstract: An integrated circuit is provided which includes a memory (100) having multiple ports per memory cell for accessing a data bit with each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plural of capacitors (102) connected together as a unitary source of capacitance (S). A first access transistor (104) is coupled between a firs one of the plurality of capacitors and a first bitline (RBL) and a second access transistor (106) is coupled between a second one of th plurality of capacitors and a second bitline (WBL) In each memory cell, a gate of the first access transistor (104) is connected to a fi wordline (RWL) and a gate of the second access transistor (106) is connected to a second wordline (WWL)

Abstract translation: 提供一种集成电路，其包括每个存储器单元具有多个端口的存储器（100），用于利用多个存储器单元中的每一个访问数据位。 这样的存储器包括存储单元阵列，其中每个存储单元包括连接在一起的多个电容器（102）作为电容（S）的整体源。 第一存取晶体管（104）耦合在所述多个电容器中的第一个电容器中，并且第一位线（RBL）和第二存取晶体管（106）耦合在所述多个电容器中的第二电容器和第二位线（WBL ）在每个存储单元中，第一存取晶体管（104）的栅极连接到fi字线（RWL），第二存取晶体管（106）的栅极连接到第二字线（WWL）

公开(公告)号：EP1661176A4

公开(公告)日：2010-03-24

申请号：EP04780833

申请日：2004-08-12

Applicant: IBM

Inventor： WANG GENG ,  MCSTAY KEVIN ,  WEYBRIGHT MARY ELIZABETH ,  LI YUJUN ,  CHIDAMBARRAO DURESETI

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/10

CPC classification number: H01L27/10876 ,  H01L21/26586 ,  H01L27/10864 ,  H01L29/1041 ,  H01L29/66537 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/945

公开(公告)号：EP1584108A4

公开(公告)日：2006-06-07

申请号：EP03701269

申请日：2003-01-08

Applicant: IBM

Inventor： MANDELMAN JACK A ,  GAMBINO JEFFREY P ,  WANG GENG

IPC: H01L21/20 ,  H01L21/308 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3081 ,  H01L27/10864

Abstract: Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.

公开(公告)号：GB2497200A

公开(公告)日：2013-06-05

申请号：GB201221408

申请日：2012-11-28

Applicant: IBM

Inventor： ZHANG YANLI ,  WANG GENG ,  MESSENGER BRIAN ,  PEI CHENGWEN ,  PARRIES PAUL

IPC: H01L27/108 ,  H01L23/48 ,  H01L23/498

Abstract: A method of forming a trench structure that includes forming a metal containing layer 20 on at least the sidewalls of a trench 10, and forming an undoped semiconductor fill material 25 in the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a second depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a first depth within the trench that is greater than a second depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill 35, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer. In one embodiment a dielectric layer 15 is deposited before the metal contacting layer, the dielectric layer is also recessed. The trench may be formed in a semiconductor 4 on insulator 3 (SOI) structure placed on a base semiconductor 2 where the second depth is within the insulator layer and the first depth is within the base layer. The trench structure may be a capacitor in a memory device with the sidewalls and base of the trench forming the first electrode and the metal containing layer forming the second electrode, an access transistor may be included. In another embodiment the trench structure is a substrate through substrate via structure where the base is planarized to expose the undoped fill material, the metal layer and the dielectric layer, an electrical structure is then bonded to the metallic structure.

公开(公告)号：GB2497200B

公开(公告)日：2014-02-05

申请号：GB201221408

申请日：2012-11-28

Applicant: IBM

Inventor： ZHANG YANLI ,  WANG GENG ,  MESSENGER BRIAN ,  PEI CHENGWEN ,  PARRIES PAUL

IPC: H01L27/108 ,  H01L23/48 ,  H01L23/498

Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

公开(公告)号：GB2497201A

公开(公告)日：2013-06-05

申请号：GB201221413

申请日：2012-11-28

Applicant: IBM

Inventor： PEI CHENGWEN ,  WANG GENG ,  RAUSCH WERNER ,  NUMMY KAREN

IPC: H01L27/108

Abstract: A trench is formed in a semiconductor substrate 8, extending through a single crystal of semiconductor material 20, and is filled with a node dielectric layer 50 and at least a doped polycrystalline semiconductor fill portion 60A, 60B. A gate stack 32, 34, 38 for an access transistor is formed on the semiconductor substrate, and a gate spacer 36 is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion, the side wall of the trench may vertically coincide with the gate spacer and may contact the gate spacer. An epitaxial source region 53 and a polycrystalline semiconductor material portion 57 overlying fill material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode. The epitaxial semiconductor material and the single crystal semiconductor material may have different lattice constants and may be n-doped, carbon doped silicon while the single crystal contains no carbon. The fill semiconductor material may be n-doped polysilicon or n-doped polycrystalline germanium. A shallow trench isolation (STI) structure may overlie the semiconductor fill material and may laterally contact one of its sidewalls. The STI structure may comprise a gate stack.