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    Method for fabricating insulated-gate field effect transistors having controlled operating characeristics
    1.
    发明授权
    Method for fabricating insulated-gate field effect transistors having controlled operating characeristics 失效
    用于制造具有控制操作特性的绝缘栅场效应晶体管的方法

    公开(公告)号：US3590477A

    公开(公告)日：1971-07-06

    申请号：US3590477D

    申请日：1968-12-19

    Applicant: IBM

    Inventor： CHEROFF GEORGE ,  HOCHBERG FREDERICK

    IPC: H01L27/088 ,  H01L29/00 ,  B01J17/00 ,  H01G13/00

    CPC classification number: H01L27/088 ,  H01L29/00 ,  Y10S438/91

    Abstract: A method for fabricating electrical circuit components, field effect transistors, for example, in which the operating characteristics of the field effect devices are tailored by eliminating or passivating surface traps along the conduction channel. A layer of an active metal aluminum, for example, is deposited on the surface of an insulator, the latter being disposed in overlying relationship with the surface of a field effect transistor which has spaced source and drain regions. The active metal is disposed between the source and drain region. The transistor is subjected to heating for a time and temperature sufficient to passivate or eliminate surface traps. By heating for a temperature in a specified range, varying degrees of passivation can be attained. Heating in the absence of metallization does not alter the operating characteristics of the insulated gate field effect transistor.

    Field effect device
    2.
    发明授权
    Field effect device 失效
    场效应装置

    公开(公告)号：US3577047A

    公开(公告)日：1971-05-04

    申请号：US3577047D

    申请日：1969-01-15

    Applicant: IBM

    Inventor： CHEROFF GEORGE

    IPC: H01L29/00 ,  H01L31/113 ,  H01L11/14

    CPC classification number: H01L31/1136 ,  H01L29/00

    Abstract: A field-effect device is provided which comprises a field effect transistor of the insulated gate type. The device is capable of being used as a photodetector with a gain greater than unity. To this end, the transistor is biased in the ''''off'''' state by a substrate potential (source-to-substrate) resulting from the provision of an external voltage supply in the source-tosubstrate loop. Upon the radiation of the source and drain junctions in the transistor, a current is caused to flow between the source and drain electrodes which result in a current gain in excess of unity.

    7.
    发明专利
    未知

    公开(公告)号：DE2001622A1

    公开(公告)日：1970-07-23

    申请号：DE2001622

    申请日：1970-01-15

    Applicant: IBM

    Inventor： CHEROFF GEORGE

    IPC: H01L29/00 ,  H01L31/113 ,  H01L11/14

    Abstract: 1276463 Photoresponsive semi-conductors INTERNATIONAL BUSINESS MACHINES CORP 6 Jan 1970 [15 Jan 1969] 571/70 Heading H1K A photoresponsive insulated gate FET comprises a P-type substrate 10 containing diffused N-type regions 12, 14 defining PN junctions 16, 18; the substrate being covered by SiO 2 layer 20. Ohmic contacts 22, 24 are made to the PN junctions which are bridged by a gate 26 overlying the SiO 2 layer. A source-drain potential source Vd is connected positively to source contact 24 and negatively to drain contact 22, while gate 26 is connected to region 12 over ohmic contact 28. Light incident on the source penetrates through regions 12 and 14 to the junctioning 16 and 18, while an external voltage source is connected positively to 22 over resistance 32 and negatively to 10 over resistance R S ; the voltage across the substrate biasing the FET "off" by substrate potential V SUB . On incidence of light from 30, the reverse bias current increases to develop a further voltage drop across R SUB formed by the geometry of the source junction, and it is shown by mathematics that current gain bandwidth is given by where g s m = substrate transconductance C = C(O)A W = channel width A = source junction area L = source-drain distance Á = surface mobility V SUB = substrate potential Vd = source/drain potential and is inversely proportional to transistor size i.e.(W/A #1/W). The source junction area may be square of side W and channel length L; the source drain and series resistance R S being formed by a shallow square diffusion permitting incident light to penetrate the surface through an anti-reflection coating (Fig. 2, not shown). In an application (Fig. 3) the phototransistor comprises gate 36 receiving signals to control current between source 38 and drain 40, and is biased "off" by V 0 over series resistor R S . A load FET 42 is connected between transistor 36 and B+ source, while FET's 44, 46 constitute an inverter driven by the combination of 36 and 42. The net current gain is given by g 8 m g g m R s 2 , where gm is transconductance of driven circuit, R SUB is determined by source junction design, and adjustment of R S varies speed of response and resistivity, so that the change in current between source and drain exceeds the change in reverse bias current. The circuit and an array of circuits may be integrated and the gate electrode may be utilized to initiate logical functions.

    FILM CONDUCTOR
    8.
    发明专利
    FILM CONDUCTOR 未知

    公开(公告)号：GB1279742A

    公开(公告)日：1972-06-28

    申请号：GB25771

    申请日：1971-01-04

    Applicant: IBM

    Inventor： AINSLIE NORMAN GEORGE ,  CHEROFF GEORGE ,  GRAFF WILLIAM SCHAMANN ,  HOWARD JAMES KENT ,  ROSS RUPERT FOSTER

    IPC: H01L21/00 ,  H01L21/28 ,  H05K1/09

    Abstract: 1279742 Semi-conductor devices; printed circuits. INTERNATIONAL BUSINESS MACHINES CORP 4 Jan 1971 [8 Jan 1970] 257/71 Headings H1K and H1R A film conductor comprises a metal containing an additive for retarding current induced mass transport of the metal. Reservoirs of the additive are disposed adjacent points where mass flux divergences, which cause depletion of the additive, occur. Such divergences occur, e.g. at interfaces with other materials in the current path and in thermal gradients. The depleted material is periodically replenished, e.g. six-monthly, from the reservoirs by heat treatment at 50-550‹ C. Typically, the conductors are of aluminium and contain copper as retardant. Iron, magnesium and silver are other retardants and the invention can also be applied to conductors of silver, gold and platinum. The conductors described constitute interconnections between integrated circuit devices formed in a silicon wafer by known planar techniques. A first layer of interconnections is first deposited over a silicon oxide, nitride or alumina passivating layer and form etched, a further layer of the insulant is then laid down, as by RF sputtering, and apertured at interconnecting points, and then a second layer of interconnections. Finally, a protective silica layer is deposited and apertured at terminal land locations where ball contacts are provided. The metal layers, e.g. of copper-doped aluminium, to which 3% by weight of silicon may be added to limit alloying to the silicon, are formed at a substrate temperature of 200‹ C. by evaporation from an alloy source, by co-evaporation from separate sources or by sequential evaporations of copper and aluminium followed by a heat treatment. Between these processes copper is deposited locally where required (see Figures, not shown) and overlain with chromium to improve the adhesion of subsequently deposited insulation. The invention may also be used with conductive films or substrates for interconnection to semi-conductor and other electronic devices.

    9.
    发明专利
    未知

    公开(公告)号：DE1277199B

    公开(公告)日：1968-09-12

    申请号：DEJ0023163

    申请日：1963-02-12

    Applicant: IBM

    Inventor： CHEROFF GEORGE ,  HOCHBERG FREDERICK ,  REISMAN ARNOLD ,  TRIEBWASSER SOL

    IPC: B22F3/10 ,  C04B35/547 ,  C04B35/64 ,  H01L21/00

    Abstract: In a sintering process, the vapour pressure of the flux used is maintained substantially constant so that the flux concentration does not decrease during the process and affect the sintering. Preferred materials are photo-conductors such as CdSe and CdS or a solid solution of both using CdCr2, CdBr2 or CdI2 as fluxes. Numerous examples are given utilizing these materials, the sintering treatments involving heating to temperatures between 522 DEG and 600 DEG C. for 5-20 minutes in an atmosphere of 0.2 to 1.7% O and the rest N and the mixtures having between 5 and 20 mol. per cent flux; grain sizes between 4 and 15 m result. Copper may be added as an impurity. The vapour pressure is maintained either by using a small volume container or by providing an auxiliary source for vapour consisting merely of the flux material or alternatively using a second supply of the mixture which is being sintered. This auxiliary source may be covered with a layer of Al2O3 which acts as a molecular sieve to govern the rate of evaporation. Fig. 3 shows a suitable small volume inner container 10 which is closed by a substrate 11 carrying on its inner surface the material to be sintered. The container is carried on an endless chain 6 in the heating apparatus shown in Fig. 2 which comprises a glove box 1 and furnace 12. Means are provided for circulating and controlling the atmosphere. When only small quantities of flux are used which are insufficient to fill the container with vapour without affecting the residue, secondary sources of flux vapour are provided in the bottom of the container 10.

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