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    Increasing resolution of on-chip timing uncertainty measurements
    1.
    发明专利
    Increasing resolution of on-chip timing uncertainty measurements 未知

    公开(公告)号：GB2577234A

    公开(公告)日：2020-03-18

    申请号：GB202000045

    申请日：2018-06-07

    Applicant: IBM

    Inventor： CHRISTOS VEZYRTZIS ,  PAWEL OWCZARCZYK

    IPC: H03K5/15 ,  G01R31/317 ,  H03K3/037 ,  H03K5/19

    Abstract: A system includes a set of delay circuits logically coupled in a chain configuration, a plurality of flip-flop circuits logically coupled to the delay output of the each of the delay circuits respectively, forming tiers of flip-flop circuits, a clock circuit logically coupled to each of the tiers of flip-flop circuits respectively, and where the plurality of flip-flop circuits is logically configured, in response to a delay input of a first delay circuit in the set of delay circuits receiving an output from a programmable delay circuit and in response to receiving skewed clock signals from the clock circuits, to indicate how far within the plurality of flip-flop circuits an edge signal transmitted from the delay output of the each of the delay circuits propagated, respectively.

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