公开(公告)号：JP2002140892A

公开(公告)日：2002-05-17

申请号：JP2001257661

申请日：2001-08-28

Applicant: IBM

Inventor： ROBERT DEAN ADAMS ,  CONNER JOHN ,  COVINO JAMES J ,  FLAKER ROY C ,  KOCH GARRETT S ,  ROBERTS ALAN L ,  SOUSA JOSE R ,  TERNULLO JR LUIGI

IPC: G06F12/16 ,  G06F12/08 ,  G11C8/10 ,  G11C15/00 ,  G11C15/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12 ,  G11C29/56

Abstract: PROBLEM TO BE SOLVED: To provide a memory system and a method in which a RAM is not required to stand by until a CAM processes a row address for a RAM. SOLUTION: This device is provided with a RAM including at least two data columns of first and second in which data is included, a gate circuit coupled to the first and the second columns and gating an output of the RAM data, and a CAM, the CAM is provided with at least two address columns including plural address positions in them, and a control circuit coupled to each address position of the first and the second address columns in the CAM and the gate circuit, sending a control signal to the gate means when a comparison address coincides with an address in the first or the second address column, and outputting RAM data from a data column address-specified by the gate means.

公开(公告)号：CA1268519A

公开(公告)日：1990-05-01

申请号：CA546779

申请日：1987-09-14

Applicant: IBM

Inventor： DREIBELBIS JEFFREY H ,  FLAKER ROY C ,  HEDBERG ERIK L

IPC: G05F3/24 ,  G05F1/46 ,  G11C5/14 ,  G11C11/407 ,  H02J3/04 ,  H02M1/00 ,  H02M1/10 ,  H03K19/00

Abstract: Power Supply Adapter Systems A power supply adapter system is provided which includes a voltage supply source terminal, an output terminal, first and second switches, the first switch being disposed between the voltage supply source terminal and the output terminal, voltage conversion means serially connected with the second switch and disposed between the voltage supply source terminal and a point of reference potential and having an output coupled to the output terminal, and means for detecting first and second ranges of voltages at the power supply source terminal and for producing first and second control voltages, respectively, to control the first and second switches. BU9-86-016

公开(公告)号：DE69216683D1

公开(公告)日：1997-02-27

申请号：DE69216683

申请日：1992-04-15

Applicant: IBM

Inventor： BONGES HENRY A ,  FLAKER ROY C

IPC: H03K17/567 ,  G11C11/413 ,  H03K19/00 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/0175 ,  G11C8/00 ,  H03K19/01 ,  H03K19/096

公开(公告)号：DE3865152D1

公开(公告)日：1991-10-31

申请号：DE3865152

申请日：1988-06-28

Applicant: IBM

Inventor： ADAMS ROBERT D ,  FLAKER ROY C ,  GRAY KENNETH S ,  KALTER HOWARD L

IPC: H03K17/08 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0948

Abstract: A CMOS off-chip driver circuit is provided which includes a first P-channel field effect transistor (32) arranged in series with a second or pull-up P-channel transistor (30) and a third P-channel transistor (36) connected from the common point (B) between the first and second transistors (32, 30) and the gate electrode of the first transistor (32). The first and second transistors (32, 30) are disposed between a data output terminal (24) and a first voltage source (28) having a supply voltage of a given magnitude, with the data output terminal (24) also being connected to a circuit or system including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. In a more specific aspect of this invention, a fourth P-channel transistor (38), disposed in a common N-well (40) with the other P-channel transistors, is connected at its source to the first voltage source (28) and at its drain to the common N-well, with its gate electrode being connected to the data output terminal.

公开(公告)号：CA1242246A

公开(公告)日：1988-09-20

申请号：CA485183

申请日：1985-06-25

Applicant: IBM

Inventor： FLAKER ROY C ,  HOUGHTON RUSSELL J

IPC: G01R31/30 ,  G01R31/28 ,  G11C29/00 ,  G11C29/04 ,  G11C29/50

Abstract: Defect Leakage Screen System A test circuit or system is provided wherein data is stored in circuits or cells of an array or matrix with the use of conventional or normal operating voltages. Voltages at internal nodes of the circuits or cells are altered to magnitudes beyond the normal operating ranges, which includes significantly decreasing the offset voltage, for a short period of time and then the stored data is read out at normal-voltages and currents and compared with the data written into the circuits or cells.