公开(公告)号：JP2002140892A

公开(公告)日：2002-05-17

申请号：JP2001257661

申请日：2001-08-28

Applicant: IBM

Inventor： ROBERT DEAN ADAMS ,  CONNER JOHN ,  COVINO JAMES J ,  FLAKER ROY C ,  KOCH GARRETT S ,  ROBERTS ALAN L ,  SOUSA JOSE R ,  TERNULLO JR LUIGI

IPC: G06F12/16 ,  G06F12/08 ,  G11C8/10 ,  G11C15/00 ,  G11C15/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12 ,  G11C29/56

Abstract: PROBLEM TO BE SOLVED: To provide a memory system and a method in which a RAM is not required to stand by until a CAM processes a row address for a RAM. SOLUTION: This device is provided with a RAM including at least two data columns of first and second in which data is included, a gate circuit coupled to the first and the second columns and gating an output of the RAM data, and a CAM, the CAM is provided with at least two address columns including plural address positions in them, and a control circuit coupled to each address position of the first and the second address columns in the CAM and the gate circuit, sending a control signal to the gate means when a comparison address coincides with an address in the first or the second address column, and outputting RAM data from a data column address-specified by the gate means.

公开(公告)号：JP2001167579A

公开(公告)日：2001-06-22

申请号：JP2000312408

申请日：2000-10-12

Applicant: IBM

Inventor： PILO HAROLD ,  COVINO JAMES J

IPC: G11C11/413 ,  G06F1/10 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

Abstract: PROBLEM TO BE SOLVED: To provide an echo-clock circuit securing accurate tracking of data transfer. SOLUTION: A comparator and a variable delay circuit are provided to keep tracking between data and echo-clock in a double data rate(DDR) RAM element. This is achieved by providing large region data signal (dummy data signal) tracking actual memory-array-data. This large region data signal is compared with a RAM clock, and a pipeline-clock (clock rise/clock fall) decides a delay time between the both to be de-layed. Conseauently, the pipeline-clock is pushed out as necessary so that it is transited after array data reaches an output latch. Therefore, when a cycle time is decreased, both of echo-clock and data are equally pushed out, and tracking re-quired for them is kept.

公开(公告)号：JPH11126484A

公开(公告)日：1999-05-11

申请号：JP22959098

申请日：1998-08-14

Applicant: IBM

Inventor： COVINO JAMES J ,  ROBERTS ALAN L ,  SOUSA JOSE R

IPC: G11C11/413 ,  G11C7/14 ,  G11C8/18 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

Abstract: PROBLEM TO BE SOLVED: To provide a memory array in which a set signal is made to follow a data signal. SOLUTION: This device has many memory cells, a set path, and at least one word line transmitting a word line selection signal to a memory cell of one row. The word line is extended to the second end from the first end of a driver. The device also has a dummy word line 20' which is extended to a point between the first end and the second end from a driver of the first end and is returned to the first end, and transmits a tracking signal responding to the word line selection signal. Thus, improved follow of a set path for a signal path can be realized by bending the dummy word line 20'.

公开(公告)号：SG77705A1

公开(公告)日：2001-01-16

申请号：SG1999003828

申请日：1999-08-05

Applicant: IBM

Inventor： BRACERAS GEORGE M ,  COVINO JAMES J ,  HEE RICHARD E ,  PILO HAROLD

IPC: G11C29/00 ,  G01R31/30 ,  G11B5/187 ,  G06F3/033 ,  G09F9/35 ,  G06F13/00 ,  G11B5/39 ,  G06F12/14

Abstract: The disclosed invention provides a circuit and burn-in test method for semiconductor devices that increases the speed of burn-in tests. The present invention accomplishes this by causing each of the devices under test to be tested multiple times (from 2 to 32+ times) during each power cycle. By such multiple cycling of the unit under test, during the power cycle, the total test time is shortened. It has also been found that the devices tested in accordance with the present invention are more efficiently stressed and have a reliability greater than devices passing the prior art tests. In accordance with the invention, the memory or logic devices under test are provided with a respective clock means that will operate each of the devices under test through multiple (from 2 to 32+ times) write and read operations during each power cycle. Data coherency for each read operation is provided as is the inversion of data if any fail is recorded during a read operation. Accordingly, the present invention provides a burn-in test that more efficiently stresses semiconductor devices such as memory or logic units, by a factor of up to 32. The invention utilizes the internal clock of a semiconductor device by cycling that clock x times during the period of each external clock cycle in the burn-in test and simultaneously synchronizes these internal cycles with the test cycle, thereby providing coherent data for each internal cycle.

公开(公告)号：MY121171A

公开(公告)日：2005-12-30

申请号：MYPI20004629

申请日：2000-10-04

Applicant: IBM

Inventor： PILO HAROLD ,  COVINO JAMES J

IPC: G11C8/00 ,  G11C11/413 ,  G06F1/10 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

Abstract: A COMPARATOR (40) AND VARIABLE DELAY (66,68) CIRCUIT ARE PROVIDED TO MAINTAIN THE TRACKING BETWEEN DATA AND ECHO CLOCKS IN A DOUBLE DATA RATE (DDR) RAM DEVICE (10). THIS IS ACCOMPLISHED BY PROVIDING A GLOBAL DATA SIGNAL (DUMMY DATA SIGNAL) THAT TRACKS WITH THE ACTUAL MEMORY ARRAY DATA. THIS GLOBAL DATA SIGNAL IS COMPARED TO THE TIMING OF THE RAM CLOCK (CLOCK) TO DETERMINE A DELAY TIME BETWEEN THE TWO BY WHICH THE PIPELINE CLOCKS (CLKRISE/CLKFALL) MUST BE DELAYED.AS A RESULT, THE PIPELINE CLOCKS ARE PUSHED OUT AS NEEDED SO THAT THEY ALWAYS TRANSITION AFTER THE ARRAY DATA ARRIVES AT THE OUTPUT LATCH.THEREFORE,AS CYCLE TIME DECREASES, BOTH ECHO CLOCKS AND DATA ARE PUSHED OUT IDENTICALLY AND MAINTAIN THEIR REQUIRED TRACKING.FIGURE 3

公开(公告)号：GB2358265B

公开(公告)日：2003-12-24

申请号：GB0024476

申请日：2000-10-06

Applicant: IBM

Inventor： PILO HAROLD ,  COVINO JAMES J

IPC: G11C11/413 ,  G06F1/10 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

Abstract: A comparator and variable delay circuit are provided to maintain the tracking between data and echo clocks in a double data rate (DDR)RAM device. This is accomplished by providing a global data signal (dummy data signal) that tracks with the actual memory array data. This global data signal is compared to the timing of the RAM clock (CLOCK) to determine a delay time between the two by which the pipeline clocks (CLKRISE/CLKFALL) must be delayed. As a result, the pipeline clocks are pushed out as needed so that they always transition after the array data arrives at the output latch. Therefore, as cycle time decreases, both echo clocks and data are pushed out identically and maintain their required tracking.

公开(公告)号：GB2358265A

公开(公告)日：2001-07-18

申请号：GB0024476

申请日：2000-10-06

Applicant: IBM

Inventor： PILO HAROLD ,  COVINO JAMES J

IPC: G11C11/413 ,  G06F1/10 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

Abstract: A comparator and variable delay circuit are provided to maintain the tracking between data and echo clocks in a double data rate (DDR)RAM device. This is accomplished by providing a global data signal (dummy data signal) that tracks with the actual memory array data. This global data signal is compared to the timing of the RAM clock (CLOCK) to determine a delay time between the two by which the pipeline clocks (CLKRISE/CLKFALL) must be delayed. As a result, the pipeline clocks are pushed out as needed so that they always transition after the array data arrives at the output latch. Therefore, as cycle time decreases, both echo clocks and data are pushed out identically and maintain their required tracking.