2.
    发明专利
    未知

    公开(公告)号:DE19614480A1

    公开(公告)日:1996-11-14

    申请号:DE19614480

    申请日:1996-04-12

    Applicant: IBM

    Abstract: The leading-zeros of a sum are determined at approximately the same time as the sum. For that purpose, the partial sums of the individual digit positions are determined in parallel, taking into account any carry digits, and potential zeros and also potential leading-zeros are predetermined based on said partial sums. When the correct value of a partial sum is determined, the potential zeros or leading-zeros are selected and if required evaluated during a subsequent step by comparison with the leading-zeros of the total sum. The leading-zeros may be determined in an adder either in a strictly parallel manner or in parallel by means of the disclosed device that has a hierarchical, iterative structure. The standardised sum may thus be optimally determined in parallel in a short time. This leading-zero determination is preferably used in adders, floating-point processors and/or data processing equipment.

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