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1.发明专利
公开(公告)号：JP2005326906A
公开(公告)日：2005-11-24
申请号：JP2004134482
申请日：2004-04-28
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： BUSADA FADI Y , GETZLAFF KLAUS , KRYGOWSKI CHRISTOPER A , SLEGEL TIMOTHY J
Abstract: PROBLEM TO BE SOLVED: To efficiently dispatch and execute a multicycle command and a complicated command in a fixed point unit (FXU). SOLUTION: In this superscalor microprocessor unit, some numbers of control signals are generated in a dispatch unit to be dispatched to the fixed point unit (FXU) together with the command, so as to dispatch and execute the multicycle complicated command. A plurality of execution pipes corresponds to command dispatch ports, and an execution unit has the fixed point unit (FXU) including three execution data flow pipes X, Y, Z and one control pipe, and executes the commands on a usable FXU pipe. Consequently, optimum performance is attained and flexibility is obtained without complicating other elements. Actual execution is carried out in the FXU not in a decode/dispatch unit without depending on decomposition by a compiler. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：在固定点单元（FXU）中有效地调度和执行多循环命令和复杂命令。 解决方案：在该超标量微处理器单元中，在调度单元中产生一些数量的控制信号，并与命令一起发送到定点单元（FXU），以便分派和执行多周期复杂命令。 多个执行管道对应于命令分配端口，执行单元具有包括三个执行数据流管道X，Y，Z和一个控制管道的定点单元（FXU），并且在可用的FXU管道上执行命令。 因此，获得最佳性能并获得灵活性而不使其他元件复杂化。 实际执行在FXU中不在解码/调度单元中进行，而不依赖于编译器的分解。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：DE19614480C2
公开(公告)日：2000-09-07
申请号：DE19614480
申请日：1996-04-12
Applicant: IBM
Inventor： GERWIG GUENTER , DAO TRONG SON , GETZLAFF KLAUS , HALLER WILHELM
Abstract: PCT No. PCT/EP95/01455 Sec. 371 Date May 13, 1997 Sec. 102(e) Date May 13, 1997 PCT Filed Apr. 18, 1995 PCT Pub. No. WO96/33456 PCT Pub. Date Oct. 24, 1996A method and apparatus for the determination of leading zero digits of a sum is presented herein. The technique incorporates the parallel determination of partial sums of single digits accounting for the possibility of carries and on the basis thereof the pre-determination of potential zero digits or potential leading zero digits. Upon the establishment of a correct partial sum, the potential zero digits are selected and evaluated thereby determining the leading zero digits. The invention may be implemented in an adder in parallel or via a hierarchical structure. The parallelism permits time-savings in the determination of a normalized sum. The invention is preferably incorporated into adders, floating point computing units and/or data processing units.
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公开(公告)号：DE19614480A1
公开(公告)日：1996-11-14
申请号：DE19614480
申请日：1996-04-12
Applicant: IBM
Inventor： GERWIG GUENTER , DAO TRONG SON DR , GETZLAFF KLAUS , HALLER WILHELM
Abstract: The leading-zeros of a sum are determined at approximately the same time as the sum. For that purpose, the partial sums of the individual digit positions are determined in parallel, taking into account any carry digits, and potential zeros and also potential leading-zeros are predetermined based on said partial sums. When the correct value of a partial sum is determined, the potential zeros or leading-zeros are selected and if required evaluated during a subsequent step by comparison with the leading-zeros of the total sum. The leading-zeros may be determined in an adder either in a strictly parallel manner or in parallel by means of the disclosed device that has a hierarchical, iterative structure. The standardised sum may thus be optimally determined in parallel in a short time. This leading-zero determination is preferably used in adders, floating-point processors and/or data processing equipment.
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公开(公告)号：AU553612B2
公开(公告)日：1986-07-24
申请号：AU1530783
申请日：1983-06-02
Applicant: IBM
Inventor： CHILINSKI HERBERT , GETZLAFF KLAUS , RAETH FRANZ JOSEF , HAJDU JOHANN
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