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    FIXING EARLY MODE SLACKS IN A CIRCUIT DESIGN
    2.
    发明专利
    FIXING EARLY MODE SLACKS IN A CIRCUIT DESIGN 未知

    公开(公告)号：GB2506275A

    公开(公告)日：2014-03-26

    申请号：GB201315088

    申请日：2013-08-23

    Applicant: IBM

    Inventor： LIND KURT ,  WOERNER ALEXANDER ,  HALLER WILHELM ,  KRAUCH ULRICH

    IPC: G06F17/50

    Abstract: Fixing an early mode slack in a hierarchically designed hardware device with at least one source macro, an integration unit and at least one sink macro. Hardware design timing data is loaded to determine pins where an early mode slack fix can be applied; for each such pin determining a location across the design hierarchy for the early mode slack fix by calculating a weight value for each of a selection of fix locations of the early mode slack based on absolute values of arrival times of data signals, ratio and difference between arrival times of late mode data signals and early mode data signals; and assigning the early mode slack fix to the determined location based on said weight value. The hardware design timing data can be filtered to determine sink macro input pins. Asssignments of critical pins to be fixed in the source or sink macro by adding delay devices or buffers may be made.

    4.
    发明专利
    未知

    公开(公告)号：DE19614480C2

    公开(公告)日：2000-09-07

    申请号：DE19614480

    申请日：1996-04-12

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  DAO TRONG SON ,  GETZLAFF KLAUS ,  HALLER WILHELM

    IPC: G06F7/485 ,  G06F7/00 ,  G06F7/50 ,  G06F7/507 ,  G06F7/74

    Abstract: PCT No. PCT/EP95/01455 Sec. 371 Date May 13, 1997 Sec. 102(e) Date May 13, 1997 PCT Filed Apr. 18, 1995 PCT Pub. No. WO96/33456 PCT Pub. Date Oct. 24, 1996A method and apparatus for the determination of leading zero digits of a sum is presented herein. The technique incorporates the parallel determination of partial sums of single digits accounting for the possibility of carries and on the basis thereof the pre-determination of potential zero digits or potential leading zero digits. Upon the establishment of a correct partial sum, the potential zero digits are selected and evaluated thereby determining the leading zero digits. The invention may be implemented in an adder in parallel or via a hierarchical structure. The parallelism permits time-savings in the determination of a normalized sum. The invention is preferably incorporated into adders, floating point computing units and/or data processing units.

    5.
    发明专利
    未知

    公开(公告)号：DE19614480A1

    公开(公告)日：1996-11-14

    申请号：DE19614480

    申请日：1996-04-12

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  DAO TRONG SON DR ,  GETZLAFF KLAUS ,  HALLER WILHELM

    IPC: G06F7/485 ,  G06F7/00 ,  G06F7/50 ,  G06F7/507 ,  G06F7/74

    Abstract: The leading-zeros of a sum are determined at approximately the same time as the sum. For that purpose, the partial sums of the individual digit positions are determined in parallel, taking into account any carry digits, and potential zeros and also potential leading-zeros are predetermined based on said partial sums. When the correct value of a partial sum is determined, the potential zeros or leading-zeros are selected and if required evaluated during a subsequent step by comparison with the leading-zeros of the total sum. The leading-zeros may be determined in an adder either in a strictly parallel manner or in parallel by means of the disclosed device that has a hierarchical, iterative structure. The standardised sum may thus be optimally determined in parallel in a short time. This leading-zero determination is preferably used in adders, floating-point processors and/or data processing equipment.

    FIXING EARLY MODE SLACKS IN A CIRCUIT DESIGN
    7.
    发明专利
    FIXING EARLY MODE SLACKS IN A CIRCUIT DESIGN 未知

    公开(公告)号：GB2506179A

    公开(公告)日：2014-03-26

    申请号：GB201217030

    申请日：2012-09-25

    Applicant: IBM

    Inventor： LIND KURT ,  WOERNER ALEXANDER ,  HALLER WILHELM ,  KRAUCH ULRICH

    IPC: G06F17/50

    Abstract: Fixing an early mode slack in a hierarchically designed hardware device with at least one source macro, an integration unit and at least one sink macro. Hardware design timing data is loaded to determine pins where an early mode slack fix can be applied; for each such pin determining a location across the design hierarchy for the early mode slack fix by calculating a weight value for each of a selection of fix locations of the early mode slack based on absolute values of arrival times of data signals, ratio and difference between arrival times of late mode data signals and early mode data signals; and assigning the early mode slack fix to the determined location based on said weight value. The hardware design timing data can be filtered to determine sink macro input pins. Asssignments of critical pins to be fixed in the source or sink macro by adding delay devices or buffers may be made.

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