公开(公告)号：US6444490B2

公开(公告)日：2002-09-03

申请号：US89470601

申请日：2001-06-28

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  FERENCE THOMAS GEORGE ,  HOWELL WAYNE JOHN ,  FIFIELD JOHN ATKINSON

IPC: H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H05K1/02 ,  H01L21/44

CPC classification number: H01L23/49816 ,  H01L23/49524 ,  H01L23/49531 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06579 ,  H01L2924/00013 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0228 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.

Abstract translation: 公开了薄膜微纤维双绞线对和其它连接器。 半导体封装包括将至少一个芯片电连接到另一层封装的微技术技术。 根据本发明的诸如薄膜双绞线对连接器的Microflex连接器提供优异的电气性能，其包括降低的线路电感，集成的无源部件的结合以及将离散的被动和有源部件附接到微反射镜。 所有这些特性使芯片在频率增加的情况下能够运行。

公开(公告)号：US6410431B2

公开(公告)日：2002-06-25

申请号：US74653400

申请日：2000-12-19

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  HOWELL WAYNE JOHN ,  TONTI WILLIAM R ,  ZALESINSKI JERZY MARIA

IPC: H01L23/13 ,  H01L23/367 ,  H01L23/48 ,  H01L21/44

CPC classification number: H01L23/13 ,  H01L23/3677 ,  H01L23/481 ,  H01L2223/6622 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2924/19104 ,  H01L2924/00014

Abstract: Through-chip conductors for low inductance chip-to-chip integration and off-chip connections in a semiconductor package is disclosed. A semiconductor device has active devices on the front surface, a first through-chip conductor having first electrical/physical characteristics passing from the front surface of the device to the back surface, a second through-chip conductor having second electrical/physical characteristics passing to the back surface, and an off-chip or chip-to-chip connector electrically connecting the active devices on the front surface to a different level of packaging.

Abstract translation: 公开了用于半导体封装中的低电感芯片到芯片集成和片外连接的芯片导体。 半导体器件在前表面上具有有源器件，具有从器件的前表面到后表面的第一电/物理特性的第一贯通芯片导体，具有第二电/物理特性的第二贯通芯片导体， 后表面，以及将前表面上的有源器件电连接到不同级别的封装的芯片外或芯片到芯片连接器。

公开(公告)号：JPH0883888A

公开(公告)日：1996-03-26

申请号：JP20688195

申请日：1995-08-14

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  HOWELL WAYNE JOHN ,  BEILSTEIN KENNETH EDWARD JR ,  DAUBENSPECK TIMOTHY HARRISON

IPC: H01L25/18 ,  H01L21/02 ,  H01L21/301 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L27/00 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a technique of selectively removing a material, which is used at the time of forming an electronic module, constituted of a 'stack' of a plurality of chips, from a cut groove region (kerf region) related to the semiconductor chips. SOLUTION: This method includes a method of providing a wafer having a plurality of integrated circuit chips having a cut groove region 17 between them. Chip metallized films 15 and 16 exist in the region 17. The wafer is protected using a photolithographic process, and only the region 17 is exposed. Then, the wafer is etched, and the chip metallized films are removed from the region 17. Then the wafer is diced, and the chips are stacked to form a monolithic electronic module. The side surfaces of the module are treated to expose a transfer metallic film which extends to the side surfaces of the module. Thereby, the electrical connection of the transfer metallic film to the chips in the module is facilitated.

公开(公告)号：ES2135507T3

公开(公告)日：1999-11-01

申请号：ES94108520

申请日：1994-06-03

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  FARRAR SR PAUL ALDEN ,  HOWELL WAYNE JOHN ,  MILLER CHRISTOPHER PAUL ,  PERLMAN DAVID JACOB

IPC: H01L25/00 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065

Abstract: A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face (16) to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer (9) is insulated from the chip face and from the adjacent chip in the stack by polymer layers (16) having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

公开(公告)号：DE69420201T2

公开(公告)日：2000-03-23

申请号：DE69420201

申请日：1994-06-03

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  FARRAR SR ,  HOWELL WAYNE JOHN ,  MILLER CHRISTOPHER PAUL ,  PERLMAN DAVID JACOB

IPC: H01L25/00 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065

Abstract: A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face (16) to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer (9) is insulated from the chip face and from the adjacent chip in the stack by polymer layers (16) having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

公开(公告)号：DE69420201D1

公开(公告)日：1999-09-30

申请号：DE69420201

申请日：1994-06-03

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  FARRAR SR ,  HOWELL WAYNE JOHN ,  MILLER CHRISTOPHER PAUL ,  PERLMAN DAVID JACOB

IPC: H01L25/00 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065

Abstract: A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face (16) to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer (9) is insulated from the chip face and from the adjacent chip in the stack by polymer layers (16) having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

公开(公告)号：AT183851T

公开(公告)日：1999-09-15

申请号：AT94108520

申请日：1994-06-03

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  FARRAR SR PAUL ALDEN ,  HOWELL WAYNE JOHN ,  MILLER CHRISTOPHER PAUL ,  PERLMAN DAVID JACOB

IPC: H01L25/00 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065

Abstract: A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face (16) to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer (9) is insulated from the chip face and from the adjacent chip in the stack by polymer layers (16) having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

公开(公告)号：SG66413A1

公开(公告)日：1999-07-20

申请号：SG1997004090

申请日：1997-11-19

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  HOWELL WAYNE JOHN ,  TONTI WILLIAM ROBERT PATRICK ,  ZALESNSKI JERZY MARIA

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L23/522 ,  H01L29/92 ,  H01L21/76

Abstract: An integrated high-performance decoupling capacitor, formed on a semiconductor chip, using the substrate of the chip itself in conjunction with a metallic deposit formed on the presently unused chip back surface and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor in close proximity to the active circuit on the chip requiring such decoupling capacitance. Specifically the present invention achieves this desirable result by providing a dielectric layer on the unused backside of the chip and forming a metal deposit on the formed backside dielectric layer and an electrical connection, between the metallic deposit and the active chip circuit via a through hole in the chip. Very precise decoupling of selected areas in the chip circuit can be achieved by forming precise and multiple metal deposits of either the same size or of varying sizes to define specific capacitances and individually connecting these deposits to the circuit areas needing the precise decoupling capacitance.