公开(公告)号：US3745539A

公开(公告)日：1973-07-10

申请号：US3745539D

申请日：1972-03-20

Applicant: IBM

Inventor： DAVIDSON E ,  LANE R ,  SAIA J

IPC: G11C11/419 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  H03K5/02 ,  G11C11/40

CPC classification number: G11C11/404 ,  G11C11/4091 ,  H03K5/02

Abstract: A semiconductor device circuit for reading an FET capacitor store dynamic memory cell and for regenerating the charge (if any) in said capacitor whereby non-destructive read-out is achieved. The memory cell includes an FET switch for selectively connecting the storage capacitor to a memory array bit-sense line through either one of a pair of oppositely connected bipolar transistors for reading and writing, respectively. The bit-sense line is connected to the input terminal of a latching regenerative feedback amplifier such as a silicon controlled rectifier. The potential level at said input terminal rises to a relatively higher level by regenerative feedback action in response to a relatively lower bit-sensing voltage which initiates the latching action. The storage capacitor of the memory cell is recharged via one of the bipolar transistors in response to the aforesaid relatively higher potential at the the amplifier input terminal. Bipolar current switch embodiments as well as a silicon controlled rectifier embodiment are disclosed for instrumenting the latching regenerative feedback amplifier.

公开(公告)号：US3761896A

公开(公告)日：1973-09-25

申请号：US3761896D

申请日：1972-04-18

Applicant: IBM

Inventor： DAVIDSON E

IPC: G11C11/41 ,  G11C11/39 ,  G11C13/00 ,  H01L21/00 ,  H01L27/07 ,  H01L27/10 ,  H01L27/24 ,  H01L29/86 ,  G11C11/34 ,  G11C5/02 ,  G11C7/00

CPC classification number: H01L27/24 ,  G11C11/39 ,  H01L21/00 ,  H01L27/0755 ,  H01L27/10

Abstract: A monolithic semiconductor memory array in which the cells comprise a voltage divider circuit formed by a fixed resistor in series with a variable switchable bistable resistor settable to either a high or a low resistance state respectively in response to the application of a pair of electrical potentials of opposite polarities.

Abstract translation: 一种单片半导体存储器阵列，其中单元包括由固定电阻器与可变可切换双稳态电阻器串联形成的分压器电路，该可变开关双稳态电阻器可响应于一对电位的电位分别设置为高电阻或低电阻状态 相反的极性

公开(公告)号：CA935887A

公开(公告)日：1973-10-23

申请号：CA100051

申请日：1970-12-08

Applicant: IBM

Inventor： MOORE R ,  DAVIDSON E

IPC: G11C11/41 ,  G11C11/39 ,  H01L27/07 ,  H03K3/35

Abstract: This application discloses a storage cell which employs a single gated multi-emitter semiconductor device that exhibits a negative resistance operating characteristic. The semiconductor device is biased to have two stable operating states on this negative resistance characteristic and is addressed by a word line connected to one of its emitters and a bit line connected to the other of its emitters. A parasitic transistor is formed by the two emitters and the gating layer of the semiconductor device. By application of half-select pulses to the word and bit lines, the parasitic transistor is broken down to cause a temporary current flow in the gating region of the semiconductor device. While this current flows in the gating region, the operating characteristic of the semiconductor device is changed so that there is only one stable operating state for the semiconductor device. The operation of the semiconductor device therefore shifts to this single operating state. When the temporary current flow ends the semiconductor device will be in a low voltage, high current stable state along the negative resistance characteristic irrespective of the operating state of the semiconductor device prior to the application of the half select pulses. When such a storage cell is manufactured in monolithic form, very high cell densities and extremely high operating speeds are obtainable.