公开(公告)号：US3745539A

公开(公告)日：1973-07-10

申请号：US3745539D

申请日：1972-03-20

Applicant: IBM

Inventor： DAVIDSON E ,  LANE R ,  SAIA J

IPC: G11C11/419 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  H03K5/02 ,  G11C11/40

CPC classification number: G11C11/404 ,  G11C11/4091 ,  H03K5/02

Abstract: A semiconductor device circuit for reading an FET capacitor store dynamic memory cell and for regenerating the charge (if any) in said capacitor whereby non-destructive read-out is achieved. The memory cell includes an FET switch for selectively connecting the storage capacitor to a memory array bit-sense line through either one of a pair of oppositely connected bipolar transistors for reading and writing, respectively. The bit-sense line is connected to the input terminal of a latching regenerative feedback amplifier such as a silicon controlled rectifier. The potential level at said input terminal rises to a relatively higher level by regenerative feedback action in response to a relatively lower bit-sensing voltage which initiates the latching action. The storage capacitor of the memory cell is recharged via one of the bipolar transistors in response to the aforesaid relatively higher potential at the the amplifier input terminal. Bipolar current switch embodiments as well as a silicon controlled rectifier embodiment are disclosed for instrumenting the latching regenerative feedback amplifier.

公开(公告)号：SE357647B

公开(公告)日：1973-07-02

申请号：SE356769

申请日：1969-03-14

Applicant: IBM

Inventor： HOFFMAN H ,  SAIA J

IPC: G05F3/22 ,  H03F1/30 ,  H03F1/32 ,  H03F3/18 ,  H03F3/195 ,  H03F3/343 ,  H03F3/347 ,  H03H11/40 ,  H03F3/04

Abstract: 1,256,736. Transistor circuits. INTERNATIONAL BUSINESS MACHINES CORP. 12 March, 1969 [15 March, 1968], No. 12907/69. Heading H3T. [Also in Division G3] The collector of each transistor 10, 12, Fig. 2, of a complementary pair is connected to the base of the other transistor and is also connected to a respective diode 15, 17, to form a three terminal network 22, 23, 25 (or 21, 24, 25, Fig. 3, not shown). The diodes may be the functions of further transistors (Figs. 1b, 1c, not shown) and each transistor 10, 12 may be replaced by a complementary pair (Fig. 1a, not shown) in which the collector of one is joined to the emitter of the other, and the base of the one to the collector of the other. Circuits employing this three terminal network are: (a) An impedance converter (Fig. 4, not shown) in which a voltage is applied (at 25) and the impedance between a terminal (22) and ground is negative and proportional to the impedance Z R between another terminal (23) and ground; (b) A voltage regulator (Fig. 5, not shown) in which a voltage is applied (at 25), a reference voltage (at 23), a start-up diode (33) is connected in the reverse direction across diode (15) and a diode (37) is connected between the output terminals (22) and 23 for overvoltage protection, the voltage across a load R1 connected at 22 being regulated. In an alternative regulator (Fig. 8, not shown) two complete networks as in Fig. 2 are connected in cascade. If I 0 rises due to a fall in load impedance R1, then the positive feedback of the circuit further increases I 0 to keep V 0 unchanged; (c) A current generator (Fig. 6, not shown) in which the current through the common terminal (25) is regulated by a reference voltage applied (at 23) through an impedance R5, the terminal (22) being grounded; (d) A differential amplifier (Fig. 7, not shown) in which a voltage is applied through impedance Rb to one terminal (25) while the voltages to be compared are applied to another terminal (at 22) and through an impedance Z r (at 23), the output Vb appearing (at 25).