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公开(公告)号：US3843954A
公开(公告)日：1974-10-22
申请号：US31996672
申请日：1972-12-29
Applicant: IBM
CPC classification number: G11C16/08
Abstract: A high-voltage integrated driver circuit for driving the word lines of a digital computer memory array of floating-gate avalanche-injection transistor memory cells, and for other applications where a high driving voltage is required. The disclosed driver circuit comprises a field-effect output transistor having a source electrode connected to a respective word line, a drain electrode adapted to have a chip select pulse signal applied thereto, and a gate electrode connected to selectably operable circuitry which may be conditioned either to a first state for clamping the voltage of the gate to cut off the output transistor and thereby maintain the output and the word line at a first voltage level, or to a second state for unclamping the voltage of the gate of the output transistor to permit the voltage of the output and the respective word line to swing with a high amplitude so as to cause the selected memory cell transistor to go into avalanche breakdown and thereby charge its floating gate so as to store a bit of information in the selected cell.
Abstract translation: 一种用于驱动浮动栅极雪崩注入晶体管存储单元的数字计算机存储器阵列的字线以及需要高驱动电压的其它应用的高压集成驱动电路。 所公开的驱动器电路包括具有连接到相应字线的源电极的场效应输出晶体管，适合于施加芯片选择脉冲信号的漏电极和连接到可选择可操作的电路的栅电极， 到第一状态，用于钳位栅极的电压以切断输出晶体管，从而将输出和字线保持在第一电压电平，或者将第二状态保持为第二状态，以解除输出晶体管的栅极的电压以允许 输出的电压和相应的字线以高幅度摆动，以使所选择的存储单元晶体管进入雪崩击穿，从而对其浮动栅极充电，以便在所选择的单元中存储一位信息。
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公开(公告)号：US3836992A
公开(公告)日：1974-09-17
申请号：US34181473
申请日：1973-03-16
Applicant: IBM
IPC: G11C17/00 , G11C16/04 , H01L21/8247 , H01L29/417 , H01L29/788 , H01L29/792 , H01L11/14
CPC classification number: G11C16/0433 , H01L29/7886
Abstract: A read-mostly memory cell is disclosed comprising a floating gate avalanche injection field effect transistor storage device equipped with an erasing electrode. The memory portion of the erasable storage devices comprises a P channel FET having a floating polycrystalline silicon gate separated from an N-doped substrate by a layer of silicon dioxide. The erasing portion of the device comprises an erasing electrode separated from the polycrystalline silicon floating gate by a thermally grown layer of silicon dioxide having a leakage characteristic which is low in the presence of low electrical fields and high in the presence of high electrical fields. The floating gate is heavily doped with boron which also partially dopes the thermally grown silicon dioxide layer. The floating gate is charged negatively by avalanche breakdown of the FET drain while the erase gate is grounded to the substrate. The floating gate is discharged (erased) upon the application of a positive pulse to the erase electrode with respect to the semiconductor substrate causing electrodes on the charged floating gate to leak through the thermal oxide to the erasing electrode.
Abstract translation: 公开了一种读出多数的存储单元，其包括配备有擦除电极的浮栅雪崩注入场效应晶体管存储装置。 可擦除存储装置的存储部分包括具有通过二氧化硅层与N掺杂衬底分离的浮置多晶硅栅极的P沟道FET。 器件的擦除部分包括通过热存储二氧化硅层与多晶硅浮置栅极分离的擦除电极，其具有在存在低电场的情况下具有低泄漏特性并且在存在高电场的情况下高的漏电特性。 浮置栅极重掺杂硼，其也部分地掺杂热生长的二氧化硅层。 浮动栅极由FET漏极的雪崩击穿负电，而擦除栅极接地到衬底。 相对于半导体衬底向擦除电极施加正脉冲时，浮栅被放电（擦除），使得带电浮栅上的电极通过热氧化物泄漏到擦除电极。
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公开(公告)号：US3745539A
公开(公告)日：1973-07-10
申请号：US3745539D
申请日：1972-03-20
Applicant: IBM
Inventor： DAVIDSON E , LANE R , SAIA J
IPC: G11C11/419 , G11C11/404 , G11C11/409 , G11C11/4091 , H03K5/02 , G11C11/40
CPC classification number: G11C11/404 , G11C11/4091 , H03K5/02
Abstract: A semiconductor device circuit for reading an FET capacitor store dynamic memory cell and for regenerating the charge (if any) in said capacitor whereby non-destructive read-out is achieved. The memory cell includes an FET switch for selectively connecting the storage capacitor to a memory array bit-sense line through either one of a pair of oppositely connected bipolar transistors for reading and writing, respectively. The bit-sense line is connected to the input terminal of a latching regenerative feedback amplifier such as a silicon controlled rectifier. The potential level at said input terminal rises to a relatively higher level by regenerative feedback action in response to a relatively lower bit-sensing voltage which initiates the latching action. The storage capacitor of the memory cell is recharged via one of the bipolar transistors in response to the aforesaid relatively higher potential at the the amplifier input terminal. Bipolar current switch embodiments as well as a silicon controlled rectifier embodiment are disclosed for instrumenting the latching regenerative feedback amplifier.
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公开(公告)号：BR7608729A
公开(公告)日：1977-10-25
申请号：BR7608729
申请日：1976-12-28
Applicant: IBM
Abstract: 1519103 Selective printing INTERNATIONAL BUSINESS MACHINES CORP 18 Nov 1976 [31 Dec 1975] 48201/76 Heading B6F Ink jet printer has pair of parallel rows of nozzles offset in the direction of their length. The jets issuing from each row are directed to different sets of non-adjacent dot positions in a row 12 and the trajectories of the jets emanating from one row of nozzles are not parallel to those of the jets emanating from the other row. The nozzles may be produced by anisotropic etching of a semi-conductor chip.
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